BSPI slave STR710FZ2T

[klavdijo]

Posted on August 02, 2007 at 16:39

BSPI slave STR710FZ2T

[klavdijo]

Posted on July 27, 2007 at 11:29

Hi,

Please someone tell me why I can't read right value from the bus. I made all steps for get right result.

CLK IN CMOS (beter electrical performance)

MISO AF PP

MOSI AF PP

SS IN CMOS

BSPI0_CSR1 |= BSPI_BSPE; // enable BSPI engine

BSPI0_CLK = 0x08; // clock devider must be more then 6 if master and 8 if slave

BSPI0_CSR1 |= BSPI_CPHA_EDGE_UP; // clock phase

BSPI0_CSR1 |= BSPI_CPOL_ACTIVE_HIGH; // clock polaryty

BSPI0_CSR1 |= BSPI_RFE_1_WORD_FIFO; // number of receiver FIFO enabled

BSPI0_CSR2 |= BSPI_TFE_1_WORD_FIFO; // number of transmitter FIFO enabled

BSPI0_CSR1 |= BSPI_WL_8; // DATA lenth in bits

BSPI0_RXR = 0; // clear receive register

BSPI0_TXR = 0; // clear transmit register

BSPI0_CSR1 |= BSPI_RIE_NOT_EMPTY; // set couse of receive interrupt

BSPI0_CSR1 |= BSPI_SLAVE; // set it to slave

communication is working with BSPI_IRQ

Properly driving SS even for every byte but no good result.

Because of low power consumption I have only 4MHz clock. Is it possible that this is wrong?

by

[klavdijo]

Posted on August 01, 2007 at 04:42

Just for info for other developers.

The problem was in initialisation for SPI0. It was my fault because i didn't read documentation well.

_set_pin(PCU_BOOTCR, BSPI0_ENABLE);

But the problem is in SPI device which can work as the master with 4MHz clock with 750k bit rate and don't work as slave with 750 k bit rate at 4MHz and I am not sure if it worke at 500 k bit rate as slave. The problem is that in documentation is not explaind the connection betwean bit rate and clock source and master or slave mode.

[javida14]

Posted on August 02, 2007 at 16:39

The master drives the clock during the 8-data bit transfer and within the select line being asserted low to the Slave. If the uP is acting as the Slave, then the external device must drive the clock and assert the SS line low to the uP. The bit rate should operate from 1Hz up to the maximum rate of either the uP or the external device (what ever is lower).