BSPI1 FIFO problem

[stonekingz]

Posted on August 01, 2006 at 10:20

BSPI1 FIFO problem

[stonekingz]

Posted on July 18, 2006 at 05:05

Hi all, I m newbie in SPI. I am facing problem with the BSPI1 here. I have 2 board right now. One is ST710 and another is cypress board. I am using SPI to connect both board together. I set cypress board as Master, ST board as slave and connect the 4 pins together.

ST Cypress

--- -------

MISO <==> MISO

MOSI <==> MOSI

SCK <==> SCK

SS <==> SS

I am testing to send 1 byte from Cypress(Master) to ST(Slave). i received correctly on the ST board. After that the problem occur when i want to send 1 byte from ST board(Slave) to Cypress board (Master). I am using the following method to send data over.

Method

======

I noticed that Slave can't generate clock if they want to send data, the clock has to be come out from Master. So i connect another GPIO to interrupt the Cypress board, when i have something to send from ST (Slave) to Cypress(Master) i just pull high the GPIO to let the Cypress know something need to send over from ST. Before i pull high the GPIO line, i set my Data(1 byte) into the transmit register first in ST. After that i pull high the GPIO. Cypress will send a dummy data(generate clock) over in order to get the data from ST. So i get the data now in Cypress Receive register.

Problem

=======

Let say, I want to send 0xA0 from Cypress to ST. ST send 0x12 to Cypress.

0xA0

1. Cypress ======> ST.

0x12

2. ST ======> Cypress.

The sequence is i send 0xA0 first from Cypress to ST. I receive correctly. Then in ST i set 0x12 into transmit register. After that i pull high the GPIO line. Cypress will send dummy data over. The problem is the data shifted out is not the 0x12, but it is the data i send from Cypress 0xA0. I use oscilloscope to see, it is 0xA0. My 0x12 only get send on the next byte. I check the status register before i want to write into the transmit register in ST and it is not FULL(TFF), i set the FIFO depth to 1 byte. I am suspecting the Shift register is not clear yet, it still contain 0xA0. Any help or suggestion ?

SPI configuration (ST BSPI1)

=================

GPIO_Config (GPIO0, 0x00F0, GPIO_AF_PP);

BSPI_Init ( BSPI1 ) ;

BSPI_ClockDividerConfig ( BSPI1,96); // 24 MHz / 96 = 250KHz

BSPI_Enable ( BSPI1 , ENABLE );

BSPI_MasterEnable ( BSPI1,DISABLE);

BSPI_ClkActiveHigh(BSPI1,ENABLE);

BSPI_ClkFEdge(BSPI1, ENABLE);

/* Set the word length to 8 bit */

BSPI_8bLEn(BSPI1,ENABLE);

BSPI_TrFifoDepth(BSPI1, 0);

BSPI_RcFifoDepth(BSPI1,0);

BSPI_RcItSrc(BSPI1, BSPI_RC_FF);

[ This message was edited by: JJz on 18-07-2006 14:06 ]

[stonekingz]

Posted on July 19, 2006 at 09:54

i have tried this setting, my problem still not solved. Any other idea ? Why the value is still keep in the shift register after i have read the receive fifo? thanx.