code in sram

[sjo]

Posted on January 15, 2007 at 12:20

code in sram

[sjo]

Posted on May 17, 2011 at 09:32

Hi,

Looking at various toolchains they all seem to use different memory address for code in sram, just wondered what is the ST preferred address for executing code in ram ?

The datasheet suggests that the AHB address should be used, but as usual the docs are very unclear.

I have executed code in unbuffered AHB and DTCM areas without problems, so the ST answer would be appreciated.

Another question a lot of the examples disable the PFQBC in the startup code, IAR/Keil as examples - could i ask why, as it is enabled by default at system reset (revD) ?

Cheers

sjo

[shangdawei1]

Posted on May 17, 2011 at 09:32

>>I have executed code in unbuffered AHB and DTCM areas without problems

which is faster ?

[amira1]

Posted on May 17, 2011 at 09:32

Hi all,

The CPU executes code from SRAM through AHB even if the DTCM is enabled. But the transfer of data can be done either from AHB or from DTCM (which is faster).

When the DTCM is disabled, all accesses to its address space go to AHB. When enabled, the DTCM must be programmed before use.

Concerning the PFQ feature, it will be enabled in the next release of “init.s� file.

Thinks and best regards,

mirou