Configurating STR750 to a SSP slave

[fabrice23]

Posted on June 21, 2007 at 00:56

Configurating STR750 to a SSP slave

[fabrice23]

Posted on June 07, 2007 at 01:25

Hello,

I'm trying to use the SSP0 of STR750 as an SPI slave.

An external 16bit ADC is the SPI master and I want to configure the STR750 as a SPI slave with following parameters.

- SS managed by software

- 16 bit data

- Data is captured on 1st clock edge(CPHA=0)

- SCK is held low when no data (CPOL=0)

- Receive Timeout interrupt(RTIM=1)

According to the datasheet(Figure 101. Generic NSS timing diagram)

Slave NSS should be pulled high between each byte transfer.

Does it mean I should control SSI bit at each byte transfer?

How can I implement this?

Here is my source code : (for simplicity, I removed some lines)

#define CR0_CPHA 0x0080 // 0=1st edge capture, 1=2nd edge capture

#define CR0_CPOL 0x0040 // 0=SCK held low when no transmit

#define CR0_16BIT 0x000F // 16-bit data

#define CR1_SSI 0x0020 // 0= slave selected when SSM=1, 1-deselect

#define CR1_SSM 0x0010 // 1= SS managed by SW

#define CR1_MS 0x0004 // 1=slave

#define CR1_SSE 0x0002 // 0=SSP disabled, 1=SSP enabled

// Motorola SPI, 16bit Data

#define SSP_CR0_INIT (CR0_16BIT)

#define SSP_CR1_INIT (CR1_SSM | CR1_MS | CR1_SSE)

Initialize()

{

// config P0.06 (MISO), P0.07 (MOSI), P0.05 (SCLK), P0.04 (NSS)

// as alternate function, push-pull

GPIO_Config(GPIO0, (GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7),GPIO_Mode_AF_PP);

SSP0->CR0 = SSP_CR0_INIT;

SSP0->CR1 = SSP_CR1_INIT;

SSP0->IMSCR |= (IMSCR_RTIM | IMSCR_RORIM);

}

SPI_Interrupt()

{

status = SSP0->MISR;

if (status & MISR_RTMIS)

{

for (i=0; i

{

Data[i] = SSP0->DR;

}

SSP0->ICR = 0; // clear flags

}

}

It doesn't work with CPHA=0.

All signals from external ADC were correct.

Please add your comments to make this code working.

Best Wishes,

Byung-Tae Jung

[kaouther]

Posted on June 07, 2007 at 14:47

Hello,

yes, you need to control the SSI bit between each byte transfer when the NSS pin is managed by software and the data is latched on 1st clock edge (CPHA=0).

- At the case the NSS pin is managed by software and data latched on 2nd clock edge ( CPHA=1), no need to control the SSI bit because the NSS internal must be held low during the entire transmission as descriebd in figure 101 in the reference manual.

- the code below will work properly if you modify the CPHA to 1 instead of 0 because you do not need to control the NSS internally.

- In the case of CPHA=0, you need to set and reset NSS pin internally between each byte as follows;

{ SSP_SendData...

SSP_NSSInternalConfig(SSP1, SSP_NSSInternal_Set); /*Set NSS internally*/

SSP_NSSInternalConfig(SSP1, SSP_NSSInternal_Reset); /*Reset the NSS internally*/

}

Hope it helps.

Regards,

[byung-tae]

Posted on June 11, 2007 at 01:26

Thank you for the reply,

My problem is for receiving data, not for sending data.

As you suggested, I tested following code for receiving.

{ SSP_ReceiveData...

SSP_NSSInternalConfig(SSP1, SSP_NSSInternal_Set); /*Set NSS internally*/

SSP_NSSInternalConfig(SSP1, SSP_NSSInternal_Reset); /*Reset the NSS internally*/

}

But it doesn't work.

How do I know a byte received in the RxFifo timeout interrupt?

According to the datasheet, I should change the NSS whenever a byte is received.

Best Wishes,

BT

[kaouther]

Posted on June 15, 2007 at 16:28

Is it possible to get the hole project? which board are using?

[byung-tae]

Posted on June 21, 2007 at 00:56

OK, here is the SPI routine.

STR755 is the slave and CS5451A(16bit ADC from Ciruus Logic) is the master.

I don't send dato to the master, only I receive data every about 500us.

My question was How can I control NSS by software whenever a byte received?

The Receive Interrupt occurs only after whole 6bytes are stored in RxFifo.

So I can not control NSS whenever a byte received.

But the datasheet says like that(Figure 101).

Maybe I misunderstood the datasheet.

Please clarify NSS control by SW for receiving data.

Thanks.

Byung-Tae Jung

________________

Attachments :

spi.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Ht9p&d=%2Fa%2F0X0000000aJj%2FaoXhDsrpeZ9l_tWWvp1qaoNUGmOW_R83RSteccjP9ak&asPdf=false