Connecting STR710 BSPI port to DSP style CODEC

[jeff1]

Posted on November 03, 2005 at 15:16

Connecting STR710 BSPI port to DSP style CODEC

[jeff1]

Posted on October 27, 2005 at 13:42

Has anyone every connected the STR710 BSPI port to a DSP type CODEC (containing MCLK, /FSYNC, SCLK, SDI, and SDO pins). We're looking into interfacing the Silicone Labs Si3000 CODEC with the STR710. According to both their datasheets the timing and waveforms are correct (or at least the STR710 BSPI port can be configured to match the waveforms that the CODEC puts out). I realize that you would have to also provide an MCLK signal to the CODEC as well (which could be provided by the STR710).

I've noticed that with SPI ports on most microcontrollers the incoming data is clocked in one side of the SCLK (trailing or leading edge) and then the outgoing data is clocked out on the opposite edge. But from what I've read in the datasheet (STR71x Microcontroller Reference Manual - March 2005 - 10352.pdf) I'm seeing that both the incoming and outgoing data can be clocked on the same edge (either trailing or leading) at the same time. Is this correct, because wouldn't that match the format that most CODEC's use as well?

I've never used an SPI port or a DSP CODEC so if anybody has any insight that would be really helpful.

Thanks in advance.

Jeff.

P.S. Here is the link to the Silicone Labs Si3000 CODEC if anyone would like to check it out:

http://www.silabs.com/tgwWebApp/public/web_content/products/Wireline/Voice_Codec/en/Si3000.htm

[scanlon]

Posted on October 28, 2005 at 15:45

We have tried a similar thing with very poor results. The port is not documented and somewhat unreliable (/SS setup times? continuous clocking? FIFO interrupts and others). I would suggest looking for another solution.

Ian

[jeff1]

Posted on October 31, 2005 at 12:50

Ian,

Thanks for your reply. Which CODEC where you trying to connect to the STR710? Also, where you able to put the CODEC in master mode and have it supply the SCLK and FSYNC signal?

I would really like to talk with you if I could, because we're about to hinge an entire product on this component arrangement. If we could save some time by learning what you learned, that would be fabulous. If you have a couple minutes to talk could you please send me your phone number to my email address at:

[e-mail]

Thank you so much.

Jeff.

[anthony239955_stm1]

Posted on November 02, 2005 at 18:08

I am looking at the same question.

In my case the Texas codec TLV320AIC20K or 24K.

ST must specify the STR7 BSPI behaviour and timing. I think it can be met, but can't be sure what I must do if I don't know what the chip requires. It is impossible to design to an interface that has no spec.

eg, in slave mode:

SCLK high period

SCLK low period

MOSI setup before SCLK

MOSI hold after SCLK

SS setup before SCLK

SS hold after SCLK

MISO delay after SCLK

MISO 3-state delays

Which clock edge is SS sampled on (depends on CPOL & CPHA?)

We assume activity on SCLK and MOSI is ignored if SS is not asserted; and that each new assertion of SS resets the shift register to start a new word.

We know that FCLK>8*SCLK but that's all. Pretty harsh as the last codec I used ran SCLK=5MHz.

The diagrams in the reference manual are wildly inacurate as in some of them a slave brings MISO out of tristate before SS is asserted! I believe it does show Rx data sampled and Tx data changing on opposite clock edges. But the statement that ''SS must be pulled low after the clock is stable'' needs consideration as codecs drive frame syncs on a clock edge.

I have used various codecs before and understand the serial communications. But I have no experience of SPI. I cannot find a published specification for SPI - the term ''SPI'' itself has no definition. It seems that each manufacturer specifies their own style of SPI - I may have used it under another guise like ''microwire''.

If the worst happens I can bit-bash the codec, if the codec will be a slave and will accept high but intermittent SCLK. One interrupt per sample of 100 instructions won't kill me it's about 3% of the CPU. Two channels is 6% - that's starting to look bad :(

The STR711 han't got many timers to burn for a sample interrupt.

Those Si3000 devices look a lot easier than the TI codecs - in fact mode 0 looks directly compatible. And 3.3V supply only. But I've never heard of the company before.

Anthony

[scanlon]

Posted on November 03, 2005 at 15:16

Hi Anthony,

I was told by ST that the /ss only acts as a gate. This is probably correct since test patterns would occasionally be split across frames. As for SiLabs, they have been around a while (and have full documentation for their parts)

Regards,

Ian

This is also from ST:

''by experiment: SS must be low before the first active clock edge. Setup time is less than 24nS. These are not the official datasheet numbers but found thru experimentation. SS must also be low during setup of the slave port library call:

/* Configure the clock to be active high */

BSPI_ClkActiveHigh(BSPI1,ENABLE);

I also found this thru experimentation.''