Daisy chained interrupt errata fix

[sjackson]

Posted on November 18, 2009 at 04:27

Daisy chained interrupt errata fix

[nle]

Posted on May 17, 2011 at 09:56

It is an interesting question. And I would like to find out also if my understanding is correct or not. Please correct me if it is wrong.

The FIQ has higher priority than IRQ so FIQ can interrupt IRQ if you do not touch the F-bit inside IRQHandler.

To prevent IRQ nesting, that is another IRQ interrupting an ongoing IRQ, you should leave the I-bit as it is inside IRQHandler and dont re-enable IRQ interrupts.

Dummy write to VIC0.VAR should be implemented in all VIC0 interrupt handler functions assigned to IRQ.

It is not necessary to read or write VIC0.VAR during an FIQ interrupt. If there is only one source, you can process the interrupt immediately. If there are more than one sources, FIQ status register must be checked to determine which one triggered the FIQ.

The current IENABLE/IDISABLE macros are intended for IRQ nesting to allow other IRQ to interrupt current IRQ. It is not needed by FIQ as it already has higher priority than IRQ.