Documentation Needs on ST33TPHF2XI2C

[erenkaya]

Hi,

We are working on a design using the ST33TPHF2XI2C TPM, and we noticed that the chip provides four GPIOs. However, there is a lack of clarity regarding their configuration and control.Clearer documentation is needed on how the GPIOs are linked to specific NV storage indices and how they can be configured or controlled through them.Is there any documentation or example showing this mapping? Additionally, could you please provide a schematic or reference design (e.g., evaluation board) and any further documentation related to the ST33TPHF2XI2C that might help?

Thank you in advance for your support.

[Peter BENSCH]

Welcome @erenkaya, to the community!

The data of all ST33 devices is strictly confidential and will only be handed over if an NDA is signed. For this reason, nobody in the public community will be able to help you, so you should contact your local ST contact.

Hope that helps?

Regards
/Peter

Thanks for your message. We'll check on the GPIO-to-NV index mapping and supporting documentation for the ST33TPHF2XI2C and get back to you shortly