EMI address bus

[stephane23]

Posted on July 14, 2005 at 16:07

EMI address bus

[stephane23]

Posted on May 19, 2005 at 10:08

Hello,

I would like to know why on the evaluation board, pin A.0 of the EMI address bus ( pin 98 IC13:STR710F ) is not connected to A.0 memory pin (pin 25 IC12: EMI flash and pin 11 IC14/15 EMI SRAM).

Schnouf

[cgrun]

Posted on May 20, 2005 at 05:21

This is done like this because the SRAM and the flash are mapped on emi as 16bit memory. The sram bank is created by two 8bit memory, but for the STR710 it is only a single bank of 16 bit memory.

You need only a0 in a bank with a memory which is wired as a 8 bit memory.

Chris.

[boppie]

Posted on July 14, 2005 at 16:07

This still has me a bit confused.

If I understand correctly, using a 16 bit EMI bus, address 0 and 1 are always =0 (STR71x reference manual rev6, p26/345 figure 3).

Why then does the STR710-EVAL schematic show A1 going to the Least Significant Address bit of the external memory devices?

Are there any other reference designs available?

Thank you for the clarification. Gone are the days where cut and jumper of engineering prototypes was only an annoyance. Now it's dang near impossible...