Ext. Interrupts with TQFP64 package?

[peterfenn9]

Posted on February 11, 2005 at 12:15

Ext. Interrupts with TQFP64 package?

[peterfenn9]

Posted on February 09, 2005 at 21:46

1) Availability of External Interrupt pins on TQFP64 package?

From page 11 to 17 of the datasheet, it appears Ext INT2, INT3, INT4 and INT5 inputs (Port 2.8 through 2.11) are not bonded out on the TQFP64 package?

- Are there any general purpose external interrupts available on this package?

2) HDLC transmit and receive clocks:

It appears there's only a single HDLC reference clock input (pin47 of TQFP64),

but register setting allows for different transmit and receive HDLC clocks?

(Presumably this only applicable if sourcing the transmit clock internally, or can an HDLC clock be sourced from another external pin?)

3) STR71x_Calculation.xls spreadsheet?

Where is this spreadsheet located?

(As described in AN2046: STR71x Clock Configurations Easy Setup)

http://www.st.com/stonline/books/pdf/docs/10842.pdf

Thanks in advance for your help on this

[hichem2]

Posted on February 11, 2005 at 11:29

Hello,Avnet_FAE,

Concerning your second question,

The HDLC Block Diagram show that each channel has its own clock line for data reception and data transmission.

Furthermore the system clock can be used both for data reception and data transmission.

The HDLC has an 12-bit Baud Rate Generator in transmission and a 8-bit Prescaler in reception.

As far as the clocking is concerned (see STR71x Microcontroller Reference Manual Rev 3, picture 86 at page 341), the clock sources can be ''HRXCK''/''HTXCK'' and they are both tied to ''PLL_HDLC_CLK'' i.e. to the output of the second PLL. In alternative CK can be selected, which is tied to ''PCLK'' (APB clock).

Max freq of PCLK is 33 MHz. Max freq. of ''HRXCK''/''HTXCK'' is 48 MHz.

I Hope that tis help you.

With regards,

HICH :p