External interrupts of ST7: How can I make sure no external edge was lost?

[johnson]

Posted on March 23, 2006 at 19:33

External interrupts of ST7: How can I make sure no external edge was lost?

[johnson]

Posted on February 28, 2006 at 06:02

In an application of my customer, he want capture four digital signals with external interrupt, by connecting the signals with pins of port B and installing interrupt routing for ei1(external interrupt 1).

He has set EICR0 register correctly and made both rising edge and falling edge sensitive,

His question is: When one signal has changed and triggered the MCU into interrupt routing, there is another signal changed closely consequently; how to make sure the last one (rising or falling edge) not be lost?

I want know that, if an edge occured closely after a edged which has make the MCU running in interrupt routing just now, would it trigger another interrupt? Will there be a pended interrupt

which will be handled after the current interrupt routing?

btw, I have read the AN1044.

[fggnrc]

Posted on February 28, 2006 at 12:34

With only one interrupt vector there is a chance that some edges will be missed.

Think at what may happen when an edge ''fires'' the ei1 interrupt handler. While the ei1 handler is running, another two edges (from different sources) re-trigger ei1. In this situation, an interrupt request is pending, but there is no way to know which input generated the request.

To miss no edge, I suggest you to use four external interrupt vectors (ei0, ei1, ei2 and ei3) which may (or may not) be implemented in the micro you choose.

Regards

EtaPhi

[johnson]

Posted on February 28, 2006 at 22:47

Hello EtaPhi:

Thanks for your help!

In fact, the question is: Does external interrupt has pending flag, and when the pending flag is cleared?

In the example you provided in the last post, while the ei1 handler is running, another two edges re-trigger ei1.

The new interrupt request is pending, of course.

IS there any pending flag which is set to indicate that there is pended request?

WILL there be another ei1 routing corresponding to the last interrupt request(It means ei1 routing will be entered again,after the current routing finished)?

If the answers of the above question were TRUE, we can check the status of the port by software, and make sure that any pulse lasted longer then an ei1 routing running time will not be missed.

By reading the datasheet, I can't get to know that, whether there are pending flags/pending bits for external interrupts? If there were, when and how the flags /bits are cleared? If the CPU is running in a interrupt disabled mode when an external interrupt required, will it serve the request after interrupts enabled?

You known, for ST7, every interrupt has its pending bit, and the bit must be cleared in interrupt routing. but external interrupts are

exceptions. If ei-x have pending flags and the flags where cleared automatically when interrupt routing entered, everything is OK.

[fggnrc]

Posted on March 01, 2006 at 04:02

As far I can know from the datasheets, the pending interrupt flag is not available to the interrupt handler (it is inside the cloud ''combinatorial logic'' that is shown in the ''I/O General Block Diagram'' figure of the datasheet).

Whenever an external interrupt handler is executed, the related flag is cleared.

To miss no edge, you have to make some assumptions on the signals (their speed, for instance) so that a falling edge may be detected by the comparison between two saved reads.

If these assumptions are sound, you must be careful to make the external interrupt handler routine (and the other ones too) as short as possible, since the code is blind (i.e. can not detect another edge) when the handler runs.

I hope I was clear...

Bye

EtaPhi

[tom_evans]

Posted on March 23, 2006 at 19:33

1 - Filter (R/C) the signal to a bandwidth where the interrupt latency guarantees service prior to the next bandwidth-limited transition.

2 - Connect to TWO pins one set to rising, the other falling.

3 - Set the pin to one edge only. In the ISR read the pin LEVEL. If it is ''the other way'' to that which caused the interrupt then you've missed the next edge (or three).

4 - Connect to two timer inputs and capture the edge transitions.