Flite 15 will not reset with watchdog

[gj2]

Posted on February 16, 2005 at 14:45

Flite 15 will not reset with watchdog

[gj2]

Posted on November 11, 2004 at 12:48

Hi,

I'm trying to get a Flite15 to reset itself, after performing an IAP update.

A little background:

The IAP code is actually copied to RAM and called as a subroutine to update one location that is a user defined configuration byte for my application. Immediately that it returns to flash based execution I try to reset the device in order to reset the RASS lock, and begin with my new configuration data.

The IAP works fine. This has been tested, and is OK. The code to perform the reset is called immediately upon completion of the IAP, and both source and the listing is shown below.

The problem is that it sits in the deadloop forever. I know this because I can monitor the port pin that is toggled - it produces a 180Hz output.

Can anyone suggest why the watchdog does not cause a reset? At the point at which this code is called it is running from flash, and should always reset. The option bytes are programmed as:

write protection off

read out protection off

Sector 0 = 1K

Oscillator = 1-2MHz LP

No reset in Halt

Software watchdog activation

LVD off

RC Oscillator ON

PLL Disabled.

The source code is:

void CPU_perform_reboot(void)

{

uint8 toggle; /* debug to see if the processor resets OK */

asm

sim

ld A, 0x80

ld 0x2e, A

endasm

for (;

{

if (++toggle & 0x80) {

PRJ_LED_VBATT_ON();

}

else {

PRJ_LED_VBATT_OFF();

}

}

}

The listing file for the above is:

1 ; C Compiler for ST7 (COSMIC Software)

2 ; Generator V4.4c - 20 Mar 2002

632 ; 66 CPU_perform_reboot(

632 ; 67 void

632 ; 68 ) {

633 switch .text

635 xref.b _CPU_perform_reboot$L

636 0000 _CPU_perform_reboot:

639 ; 77 sim

642 0000 9b sim

644 ; 78 ld A, 0x80

647 0001 a680 ld A, 0x80

649 ; 79 ld 0x2e, A

652 0003 b72e ld 0x2e, A

654 0005 L353:

655 ; 82 if (++toggle & 0x80) {

657 0005 3cff inc _CPU_perform_reboot$L-1

658 0007 b6ff ld a,_CPU_perform_reboot$L-1

659 0009 a580 bcp a,128

660 000b 2704 jreq L753

661 ; 83 PRJ_LED_VBATT_ON();

663 000d 1800 bset _PADR,4

666 000f 20f4 jra L353

667 0011 L753:

668 ; 86 PRJ_LED_VBATT_OFF();

670 0011 1900 bres _PADR,4

671 0013 20f0 jra L353

683 xdef _CPU_perform_reboot

702 end

Any help will be much appreciated.

[wolfgang2399]

Posted on November 12, 2004 at 05:51

Hi glec,

did you wake up the watchdog?

Reset value of the watchdog timer register WDGCR is 7Fh. That means, the WDGA flag is cleared and the watchdog function disabled. You have to activate the dog by setting the WDGA flag e.g. writing a FFh to the WDGCR.(See also chapter 11.1 in the manual)

Regards, WoRo

[gj2]

Posted on November 13, 2004 at 10:38

Hello WoRo,

Thanks for your input. Yes, I have written to the WDGCR - in fact I have tried many values. I set bit 7, and also many combinations of the others. The example code I posted actually contained the assembler instructions that I had substituted in case the label I previously used was pointing to the wrong register.

In this case I was writing 0x80 to the WDGCR (address 0x2e). According to the datasheet this should cause an immediate reset.

Sorry if my code was not clear - I just copied my most recent code in there, and forgot it was not the more descriptive C code instead. Also I failed to get the formatting right!

Interestingly the reset actually works when I let the Softec InDart tool run through it. It stops running at an automatic breakpoint at the start of the code.

I'll keep looking and trying a few variations.

Once again many thanks.

[wolfgang2399]

Posted on November 15, 2004 at 05:27

Hi glec,

sorry, I missed out on the fact 0x2e is the WDGCR. Your code seems to be allright.

I have no idea in relation to the software. In my application (with a FLite29) I force a reset exactly as you do with

while (1);

compiled to

021f 20fe JRT *0 ;abs = 021f

and it suites.

The last idea I have is to check the reset pin. Do you drive it with an external hardware? If the reset pin is driven by a low resistance source e.g. strongly tied to Vdd or with a pushpull driver the internal FET can't pull it down to the reset state.

Best regards, WoRo

[gj2]

Posted on February 16, 2005 at 14:45

***** SOLVED *****

I won't bore everyone with the saga, but it now works.

Code was OK - it appears to be the settings of the programmer. I was using a Softec InDart, and datablaze allows you to set all the option bits individually.

I was using the internal RC in LP mode and PLL disabled. It was found that with the PLL multiplier of x4 caused a problem - and x8 was OK. Odd.

/\/\/\/\/\ Many thanks to SJO for that one. /\/\/\/\/\