Glitch at Port9

[hancicimen]

Posted on April 17, 2008 at 11:27

Glitch at Port9

[hancicimen]

Posted on May 17, 2011 at 09:51

Hi,

I am developing a software for graphic lcd like application. 8 pins are set at GPIO8 as pushpull output and 4 pins are set as pushpull output at GPIO9.

When I write

GPIO_Write(GPIO8,0xff);

LCD_CtrlLinesWrite(GPIO9, LCDCLK, Bit_SET);

LCD_CtrlLinesWrite(GPIO9, LCDCLK, Bit_RESET);

GPIO8->DR[0x3FC] =0x0;

I can see a very high frequency glitch ( may be >50 mhz I can not see it exactly from the scope) at outputs of Port9 after I write 0x0 to GPIO Port 8. I can barely see it from the my Scope and but STR9 is attached to a FPGA from this pins, and FPGA can sense this glitch. (infact thats how I could notice this situation) I write different values than 0xff for the first write, and it seems like this reduce to frequency of glitch but not totally eleminated. I wonder how could this happen or where do I wrong?. I just write a simple filter in the FPGA and it solved all the problem. I plan to use this ports for other purposes ,so this is very strange situation for me.

Best regards,

HAN

[kais]

Posted on May 17, 2011 at 09:51

Hi,

This crosstalk phenomenon already exists in all PCB designs

but with different scales.

So it's obvious,switching the state of one IO can affect other IOs

Anyway this can be with small effect when your PCB is designed for EMC.

Eris.

[hancicimen]

Posted on May 17, 2011 at 09:51

Thanks for the info. I use MCBSTR9 and hope it is problem of this board and it is only crosstalk.

Best regards,

HAN