Hi, I'm using EEPROM M95080. It is mentioned that the IC will send data at the falling edge. But its not happening exactly at the falling edge(there is a delay of almost 0.2 microseconds after the falling edge).

[PTiwa]

1)The IC supports both the modes of SPI(CPOL =1,CPHA =1 and CPOL =0,CPHA =0). On the master side I have configured the SPI with CPOL = 1and CPHA = 1.

2) According to this master SPI mode the master will receive data at the rising edge and the slave sends it at the falling edge(here is a delay of almost 0.2 microseconds after the falling edge).

3) I have written the status register with the data 0x0C and then I read it. In the SPI receive buffer I read it as 0x0C but on the oscilloscope its something different.

In the scope images shown below:

Green: Chip Select

Yellow: Clock

Pink: MOSI

Blue: MISO

Attached are the scope images.

The first image shows the data on MISO line which is expected to be 0x0C.

The second image also shows data on the MISO line with a delay of almost 0.2 microseconds after the falling edge

[Pierre P.]

​Hello,

Intrinsic value @25°C @5V characterized during the qualification shows around 20ns.

Image 1 shows intermediate value which is not correct. The MISO value must be @Vcc when outputting the "1".

Please verify there is no conflict on MISO line & check if the master doesn't drive the MISO line at the same time than the slave.

BR

EEPROM suPPort Team

[PTiwa]

Hi,

Thanks for the reply. The delay that i mentioned is not there when i change the master mode from CPOL = 1 and CPHA = 1 to CPOL= 0 and CPHA = 0(which is quite surprising as these modes are almost same).

The main problem that I have at the moment is that the eeprom transmits data at the falling edge and the master ​reads it at the rising edge.

The master(stm32 controller) has to read it at rising edge because of the supported modes of the eeprom ic(eeprom ic can receive data at the rising edge) in both of which master sends and receives data at the rising edge.​