How many sample times when ST7L09 check 1 bit on its MISO pin?

[jacktan1]

Posted on December 11, 2003 at 22:26

How many sample times when ST7L09 check 1 bit on its MISO pin?

[jacktan1]

Posted on December 06, 2003 at 07:00

How many sample times when ST7L09 check 1 bit on its MISO pin during SPI com?

I m eager to know the answer. If there is no sample, how SPI gives user a strong safety of its SPI?

[jatin]

Posted on December 09, 2003 at 07:10

There is no sampling done during SPI reception as data is latched with the clock edge.

There are three error flags available inside the control/status register.

[jacktan1]

Posted on December 10, 2003 at 00:07

Thank you Jatin!

I m now working on a project which uses ST7L As you know, the MCU has only 1.5K program ROM, and has no Asyn com port. I have to design software to emulate the com port. I thought I m very clever

, 'cause I use the SPI port to solve the problem. But I m not sure if the method is safe enough. The com protocol is 1 STRAT bit followed by 8 bit data and then VERIFY bit, STOP bit. When the falling down edge of the start bit received, an interruption is genarated, then the SPI started. The SCLK for SPI is genarated by a IO pin, it is timer controlled by AT. By this way, the VERIFY bir is ignored.

Do you agree with me? Do you have any better way to solve the asyn com? Thank you!

[jatin]

Posted on December 10, 2003 at 07:15

There is one application note available (AN1753 - Software UART using ST7 12-Bit Autoreload Timer). It is downloadable from the same site.

[jacktan1]

Posted on December 11, 2003 at 06:09

OK, I have read the doc. Thanks a lot!

Now I meet a question:

As you know, when the falling edge of the START bit, an interrupt is generated. According to the doc, I should start the OUTPUT COMPARE immediatly. NOTE pls: we dont know the value of 12 UPCOUNT counter exactly at this moment. so we can not calculate the exact time delay for ''half bit''. For example, if at this moment the UPCOUNT counter contains value of 0x683, we set the DCR0 to 0x682, the time will delay up to 0xfff cycles, not 0x682 cycles . it s ERROR!

So what can I do?

Best Regards,

J.V.

[jatin]

Posted on December 11, 2003 at 11:09

Hello,

The sequence in START interrupt is:

+ Set counter for half bit delay (note: it is relative so you are supposed to add it in present CNTR value).

+ Set DCR0x for next bit delay (according to above calculation)

+ Disable ext. interrupt

+ Set clock & enable output compare interrupt

I

[jacktan1]

Posted on December 11, 2003 at 22:26

Thank you!

I got it!

It s veru helpful for me.