How to partition program space and Data space?

[deng]

Posted on May 12, 2004 at 22:32

How to partition program space and Data space?

[deng]

Posted on May 17, 2011 at 12:00

Hi All,

We have the following mapping in the uPSD3254BV:

RS0 0x0200 -> 0x7FFF (data space)

CSIOP 0x0100 -> 0x01FF

FS0 0x8000 -> 0xFFFF (program & data space)

FS1 0x8000 -> 0xFFFF (program & data space)

: : (program & data space)

FS7 0x8000 -> 0xFFFF (program & data space)

CSBOOT0 0x0000 -> 0X1FFF (program space)

CSBOOT1 0x2000 -> 0x3FFF (program space)

CSBOOT2 0x4000 -> 0x5FFF (program space)

CSBOOT3 0x6000 -> 0x7fff (program space)

The question is how do we allocate the primary flash

when we set it to both program and data space. Could

it be actually allocate the full 256K of 8 pages to

program space and leaving nothing to Xdata space.

Hence there is nothing above the 32K data space (RS0/SRAM)?

Is there any way to tell the MCU to partition the memory to

program or data space? We want the data to be nonvolatile memory.

Any ideas?

SD

[lwang]

Posted on May 17, 2011 at 12:00

You cannot map all 256KB of Primary Flash into 32KB (0x8000 => 0xFFFF) of program/code space at the same time. However, you can break up the 256KB into 8 pages of 32KB each and map one of the pages at a time.

For example:

page=[pgr2..pgr0];

FS0 0x8000 -> (0xFFFF (program & data space) & (page==0);

FS1 0x8000 -> 0xFFFF (program & data space) & (page==1);

: : (program & data space)

FS7 0x8000 -> 0xFFFF (program & data space) & (page==7);

P.S. You did not map anything to 0000->00FF in data space.

[deng]

Posted on May 17, 2011 at 12:00

Thanks for the replay. I understand we need to break-up the 265K into 8 pages. What I was wondering is how does each of the memory bank partition. For example on page0 (FS0:

FS0 0x8000 -> (0xFFFF (program & data space) & (page==0);

Which memory locations are allocate to program space and which are allocate to data space? Is there anyway to control the partition? For example, can I allocate 0x8000 -> 0XAFFF for program space and the rest of the for data space?

I hope this will clear-up my question.

Regards,

SD

[lwang]

Posted on May 17, 2011 at 12:00

Sector Select (FS0..7) normally only controls the address range. Whether that Sector is mapped to Code or xData space (or both) is controlled by 2 individual bits in VM Register. Thus when a Sector appears in both Code and xData space, normally the address range in Code space is the same as the address range in xData space. For example:

FS0 = ((address >= ^h8000) & (address <= ^hFFFF));

When VM enables Primary Flash in both Code and xData, you get:

Code 8000-FFFF = FS0

xData 8000-FFFF = FS0

However, CSBOOTx, CS0, or CSIOP may overlaps with FSx and take away the overlapped address range. This is because they have higher priority than FSx.

We can have, in addition:

CSBOOT0 = ((address >= ^hB000) & (address <= ^hBFFF));

CSBOOT1 = ((address >= ^hC000) & (address <= ^hDFFF));

CSBOOT2 = ((address >= ^hE000) & (address <= ^hFFFF));

CS0 = ((address >= ^h8000) & (address <= ^hAFFF));

When VM enables (a) both Boot Flash and Primary Flash in Code space, and (b) both SRAM and Primary Flash in xData space, you get:

Code 8000-AFFF = First 12KB of FS0

B000-BFFF = Part of CSBOOT0

C000-FFFF = CSBOOT1, 2, and 3

xData 8000-AFFF = Part of SRAM

B000-FFFF = Rest of FS0

This will split FS0 into two parts as you requested. But I do not see any advantage of doing so.

[deng]

Posted on May 17, 2011 at 12:00

Thanks for the replay. The reason we want to split the main flash to program and data space is that we do not want to use the SRAM for data storage since it's a volatile memory. Also, we need more than 32K of data space.

In your replay, there is a ''CS0 = ((address >= ^h8000) & (address <= ^hAFFF)); ''. Any idea what that is? How do I get that set in PSDsoft? Is this the allocator?

Regards,

SD

[lwang]

Posted on May 17, 2011 at 12:00

Sorry, the ''CS0'' was a typo. It should have been ''RS0''. That reply was just to illustrate that indeed you can partition a Primary Flash so that part of it appears in Code space and the remainder appears in xData space. But that scheme was too complex and there is no practical advantage of using such a scheme.

To achieve what you want to do, your original logic equations, with the additional ''page'' term, are fine. Any of the Primary Flash sectors can be accessed one at a time (with the page register). If that sector has Code, you can enable it in Code space. If that sector has data, you can enable it in xData space. If part of that sector has code and the rest of it has data, you can enable it in both Code and xData spaces. (Your software must not try to run code in the data part or write data into the code part.)

[deng]

Posted on May 17, 2011 at 12:00

Hi,

Thanks for the respond. Now, we go back to my original mapping, which are:

RS0 0x0200 -> 0x7FFF (data space)

CSIOP 0x0100 -> 0x01FF

FS0 0x8000 -> 0xFFFF (program & data space)

FS1 0x8000 -> 0xFFFF (program & data space)

: : (program & data space)

FS7 0x8000 -> 0xFFFF (program & data space)

CSBOOT0 0x0000 -> 0X1FFF (program space)

CSBOOT1 0x2000 -> 0x3FFF (program space)

CSBOOT2 0x4000 -> 0x5FFF (program space)

CSBOOT3 0x6000 -> 0x7fff (program space)

I am able to write data to the SRAM (RS0 0x0200 -> 0x7FFF ) without any problems. THe problem now is I can't write Xdata to the main flash (FS0-FS7). For example, I can not write to location 0x8000. The main flash is set to ''both program and data space''. This should be a very basic setting.

On page 33 of the PSDSoft express user manual ''http://www.st.com/stonline/books/pdf/docs/8139.pdf'', it says something about adding user control signals to control the combine FS0-FS7. Can somebody please let me know how this work? None of the examples I got has the main flash in both program and data space. I would think PSDsoft would take care the mapping once we selected the ''both program and data space'' for the main flash, but there is more to it and it's very confused.

Please help!

SD

[lwang]

Posted on May 17, 2011 at 12:00

To achieve what you want to do, your original logic equations, WITH THE ADDITIONAL ''PAGE'' TERM, are fine. You forgot the ''page'' term again. You cannot map all 8 sectors of Primary Flash EPROM into the same 32KB of 0x8000-0xFFFF all at the same time. Besides the ''page'' term, you do not need to add anything else to FS0-FS7.

In order to make one of these 8 sectors appear in xData space, you need to write its ''page'' number into the page register and set bit-4 of VM register to 1. After you have done all the above, you will be able to ''read'' its content by ''reading'' from it, but you still cannot change its content by simply ''writing'' to it.

The acronym EPROM stands for ''Erasable Programmable Read Only Memory''. In order to change the content of Flash ERROM, you need to ''erase'' and/or ''program'' it. Other than erase/program, it is ''Read Only'' and cannot be ''Written''. The uPSD32xx datasheet has Sections about ''Programming Flash Memory'' and ''Erasing Flash Memory'' under ''MEMORY BLOCKS''.