I2C mastertransmit/receive

[el_kloklo]

Posted on October 03, 2008 at 13:13

I2C mastertransmit/receive

[el_kloklo]

Posted on October 02, 2008 at 14:20

Hello all, i'm writing here because i've got little problem to use my i2c device as master on my microcontroller.

I'm using a ST EMU3 Emulator.

My code is as following, using interruption :

Code:

Initialize

read SR1 register

read SR2 register

set PE bit on CR register (must be initialized two times, as describe in datasheet)

set PE and ITE bit on CR register (allow interrupts and I2C)

set 0x7f on CCRregister (max clock divider)

set 0 on OAR2 (freq CPU<6Mhz)

clear ACK, START, STOP bit in CR register

Start communication

set packet_idx to 0

launch initialize function

set START bit in CR register

interruption (vector 12)

if EVF bit in SR1 is set (event happened)

{

if SB is set in SR1 is set (start bit correctly generated)

{

copy SR1 register in a buffer variable (clean SR1)

copy adress + read/write bit in DR register

}

else

{

if BTF bit in SR1 is set (packet correctly transmitted)

{

if state is writing (internal variable)

{

if packet_idx < qtty of data

{

read SR1 register in a useless buffer

copy data buffer at position packet_idx into DR register

increase packet_idx

}

else

{

set bit STOP in CR

unset bit PE in CR (disable the device)

}

}

else

{

if packet_idx < qtty of data - 1

{

set ACK bit in CR

read SR1 in an useless buffer

read DR in the data buffer

increase packet_idx

}

else

{

set STOP bit in CR

unset PE bit in CR (disable the device)

read DR in the data buffer

}

}

}

else (note : this case happen only in receive, and after the transmit of adress)

{

set ACK bit in CR register (if i don't do this ack, slave don't transmit anymore)

read SR1 in an useless buffer

set PE in CR register (already set, but it is specified in datasheet that's the only way to clean this interrupt)

}

if BERR, AF or ARLO bit in SR2 is set

{

clear Pe bit in CR

}

}

}

this code work well in transmit, but in receive, only the first train is correctly send, data line remain low, even if the stop bit is correctly run, and no more i2c event happen, even if a new transmission is initiated.

Well, thanks for advice, and see you.

[el_kloklo]

Posted on October 03, 2008 at 07:07

well, with more details, i could say that the stop is not correctly generated (even if the instruction is runned) in master receive mode, so the bus is never free, even if it is disabled.

[el_kloklo]

Posted on October 03, 2008 at 13:13

solved myself. It's written to generate non ack just before reading I2C data register on the before ultimate and ultimate byte of the packet.