I2C slave transmission

[jens239955_stm1]

Posted on March 01, 2007 at 15:19

I2C slave transmission

[jens239955_stm1]

Posted on May 17, 2011 at 09:39

Hi,

I try to use the I2C interface of the STR912 in slave mode. The communication in the slave receiver mode looks like o.k. But the slave transmitter mode generate errors.

The STR9 documentation describe the slave transmission procedere as followed:

S ADRESS A DATA1 A DATA2 A DATA NA P

EV1|EV3 EV3 EV3 EV3-1 EV4

EV1 : EVF = 1, ADSL = 1; cleared by reading I2Cn_SR1 register

EV3 : EVF = 1, BTF = 1; cleared by reading I2Cn_SR1 register, following by writing DR

EV3-1 : EVF = 1, AF = 1, BTF = 1; AF is cleared by reading SR2, BTF is cleared by releasing the line or writing DR = 0xff

EV4 : EVF = 1, STOPF = 1; cleared by reading SR2

In my opinion the EV3-1 has to be detected by reading SR1 und SR2 registers and testing the AF and BTF bits. With other words the following code snipped have to do that work:

if((I2C0_SR2 & I2C0_SR2_AF) && (I2C0_SR1 & I2C0_SR1_BTF)){ /* Not ACK -> EV3-1 */

I2C0_DR = 0xff;

.....

This condition was never reached !!! Instead of the BTF the BUSY bit was set!

That's why I changed the test to

if(I2C0_SR1 & I2C0_SR2_AF){ /* EV3-1 */

I2C0_DR = 0xff;

.....

Now I got the AF condition and I would expect that the EV4 (STOPF condition) was the next (last) event during I2C slave transmission.

These condition fails sometimes. Note: sometimes !!!

To verify the effect I wait into the interrupt service routine (very dirty I know) to the next event bit (I2C0_SR1 & 0x80). The event occurs but the STOPF bit in the SR2 was not set. The SR1 register contains 0xb8 -> EVF, TRA, BUSY and BTF is set. The EV3 is also upcoming? So I wait for the next event and now I found the EV4.

In the result the slave transmission sequence has an addional event EV3 (look below):

S ADRESS A DATA1 A DATA2 A DATA NA P

EV1|EV3 EV3 EV3 EV3-1 EV3 EV4

Is this correct?

Best regards,

Jens