Incorrect action of bridges in STPC VEGA

[granitvt]

Posted on December 20, 2004 at 22:07

Incorrect action of bridges in STPC VEGA

[granitvt]

Posted on September 30, 2004 at 04:20

I have module based on STPCV1JEBC chip (further - CHIP). After end of reset (PWROK going active) I see (using logic analyzer) on PCI bus following diagram: 1. address FFFFFFFxh (or 000F00xx - after far jump), active FRAME#, C/BE[3..0] - 6, after - active IRDY#, C/BE[3..0] - 0 but not active DEVSEL# (and STOP# and TRDY#); or 2. address FFFFFFFxh (or 000F00xx - after far jump), active FRAME#, C/BE[3..0] - 6, after - active IRDY#, C/BE[3..0] - 0 active DEVSEL# but not active STOP# or TRDY# (CHIP deadlock). But I see memory cycles on ISA bus to the BOOT FLASH. What is it ???

P.S. I have only one CHIP on PCI bus, no more devices. I use recommended schematic, 2 CHIPs and many alternate schematics for cover this problems.

Best regards.

[kaouther]

Posted on December 20, 2004 at 07:00

At the boot, the CPU fills its first cache line by fetching 16 bytes from boot memory this is what you see ''The memory cycles on ISA bus to the BOOT FLASH''.

[twitwity]

Posted on December 20, 2004 at 22:07

hi,

although it wouldn't do much at chip boot time, the datasheet sould have the exact sequence of signals. it is too brief and abstract.

just 2 weeks ago, i have been experienced that kind of stuff and my board passed through BIOS boot, now im trying the OS loading.

yes, things should go right and all the clocks shows right timing and flash CS signal actibity shown , signal activities on PCI shown, memory cycles are activated, but one thing. there are much wide gaps to overcome between flash signal activity and all other bus signal probing. data sheet should give sample timing diagram and relevant timing sheet to be an actual aid to any engineer.

(well if you ST guys have some time to spare, have and refer to PLX devices datasheet. it is damn good with abundant diagrams and 'real data'.. you don't even have actual power dissipations in data sheet.. saying it is not so hot.. yes it is not very hot when it is not actually working,.. may down the HCLK, PCI CLK, memory CLK...)

BTW, when will you plan to ship the 'real commercial version' of this CPU to the market?

* I think, user, before actuall BIOS codes in FLASH loaded into RAMs and be decoded and program all the registers and get the chip ready, all the sequence of any protocol would be considered meaningless..