Interrupt ST7FLITE09

[msteinhart]

Posted on May 03, 2004 at 12:11

Interrupt ST7FLITE09

[msteinhart]

Posted on April 28, 2004 at 12:13

Hi everybody,

here is a problem, I try to use the LT timer (ST7FLITE09) .

Everything is OK if the Watchdog is switched off, but with the WDG enabled

(and cyclically resetting it in the main loop) the following occurs:

- every 33ms there was a missing LTtimer interrupt

- by switching off the WDG the problem was gone

- switching on the ARTimer changes the extint, that it looks like low

level

Does this controller not work with this conditions?

Thanks,

Metabo_ms

[jatin]

Posted on April 29, 2004 at 10:16

The problem is when you are refreshing the watchdog by setting the WDGD bit (i.e delay the watchdog reset) , you are clearing the TBIE interrupt enable bit. Use the instruction LTCSR = 0x13 to refresh the watchdog timer.

[msteinhart]

Posted on April 29, 2004 at 13:30

Hello Jatin,

thanks for the answer, but sorry nothing changed in the programm!?!?!?

The attached programm shows a

- LTtimer with interrupt request

- ART Timer with interrupt request

- External interrupt ei0

The processor doesn't work well,

It always reset,

no LT Timer interrupt

external interrupts during the complete low level time

no ART Timer interrupt

Is it the processor?

Thanks for answering,

Metabo_ms

The attachment doesn't work, sorry:

include

include ''lib_bits.h''

define sim() _asm(''sim'') //Set interrupt mask

define rim() _asm(''rim'') //Reset interrupt mask

@interrupt void lt_ovf(void)

{

unsigned int a;

SetBit(PADR,5);

a=LTCSR; // reset TBF

a=LTICR; // reset ICF-Bit

ClrBit(PADR,5);

}

@interrupt void ext_0(void)

{

SetBit(PADR,7);

ClrBit(PADR,7);

}// ir ext_0

@interrupt void at_ovf(void)

{

unsigned char a;

SetBit(PBDR,2);

a=ATCSR; // reset ART OVF Flags

ClrBit(PBDR,2);

}// at_ovf

void main(void)

{

unsigned char i;

_asm(''ld A,0xFFDE''); // Definition der Pointerszm Memory Lage

_asm(''ld 0x39,A''); // fuer die RC calibrierung

//Portinit

PADDR=0xFE; // PORTA: bits 0..6 (output=1)/ 7 Input

PAOR=0xFE; // PushPull--> PA7 -Floating-see Extinit!

PADR=0x00; // Outputs 0

PBDDR=0x1F; // Port B: bits 0..2 (input=0)

PBOR=0x1F; // Pullup

PBDR=0x00; // Outputs 0

// Timerinit

i=LTICR; // Reading LTICR

i=LTCSR; // Reading LTCSR

ClrBit(LTCSR,2); // WDG Reset Status Flag

LTCSR=0x12; // (2ms@8MHz), int aktiv/WDG enable

// Autoreload Timerinitialisierung

i=ATCSR; // reading ATCSR

ATCSR=0x12; // Counter Clock=fcpu/ OVF Int enable

ATRH=0x0B; // Counter value of the Reload Registers

ATRL=0x1E; // (60us-0E8F)(120us-0D40)(180us-0C56)(156us-0C6E)

ClrBit(PWM0CSR,0); // Upcounter val. doesnt match DCR val

ClrBit(PWMCR,0); // PWM0 output enabled

// External Interruptinit

sim(); // disable interrupts

EICR=0x03; // ei0-->neg & pos edge (PA0)

rim(); // enable interrupts

SetBit(PAOR,0); // ExtInt0 enable (pushpull)

SetBit(PBDR,0); // Indicate booting

ClrBit(PBDR,0); // Indicate booting

SetBit(PBDR,0); // Indicate booting

ClrBit(PBDR,0); // Indicate booting

SetBit(PBDR,0); // Indicate booting

ClrBit(PBDR,0); // Indicate booting

SetBit(PBDR,0); // Indicate booting

ClrBit(PBDR,0); // Indicate booting

for(;

// Neverending loop

{

SetBit(PADR,1); // control on

LTCSR=0x13; // Refresh the Watchdog Timer

ClrBit(PADR,1); // control off

}//for

}//main

/*Outputs************************

PA0 --> Input for extint0 i.e. square waveform

PA1 --> High during the neverending forloop

PA5 --> LT-Timer Interrupt is running

PA7 --> Extintroutine is running

PB0 --> Indicate booting pin

PB2 --> ART-Timer interrupt is running

*/

[ Diese Nachricht wurde editiert von : metabo_ms on 29-04-2004 17:04 ]

[msteinhart]

Posted on May 03, 2004 at 12:11

Hey all,

I found the solution myself! My linkfile had a mistake! Now it works.

Thanks

[ Diese Nachricht wurde editiert von : metabo_ms on 04-05-2004 08:44 ]