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jgil
Visitor II
May 22, 2003
Question

Interrupts trigger in uPSD

  • May 22, 2003
  • 2 replies
  • 575 views
Posted on May 22, 2003 at 16:30

Interrupts trigger in uPSD

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    2 replies

    J
    jgilAuthor
    Visitor II
    May 17, 2011
    Posted on May 17, 2011 at 11:54

    hi,

    I need some more information regarding the interrupts triggering in the uPSD3200 .

    I don't know if INT0 and INT1 are triggered by positive level/edge (refer to page 38 of the uPSD321x data sheet ) or they're triggered by negative level/triggered ( refer bit IT0 of the register TCON at the table37 of datasheet).

    Thanks in advance for any comments.

    Regards,

    Jokin

    J
    joseph2399
    Visitor II
    May 17, 2011
    Posted on May 17, 2011 at 11:54

    Hi,

    According to Table 37, when IT0 bit is SET, INT0 is triggered at the falling-edge. When IT0 bit is CLEARED, INT0 is triggered at the low-level. IT1 control bit works the same way for INT1.
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