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bleumers_j
Visitor II
October 5, 2004
Question

LVD / external reset

  • October 5, 2004
  • 8 replies
  • 1734 views
Posted on October 05, 2004 at 12:42

LVD / external reset

    This topic has been closed for replies.

    8 replies

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    bleumers_jAuthor
    Visitor II
    October 1, 2004
    Posted on October 01, 2004 at 12:08

    Hi everyone,

    I'm doubting about the way to manage the reset of a MCU.

    Untill now i've used the LVD at 4,1V and left the reset pin at the Vss. I never had any trouble with this.

    But is this the best way or is an RC reset-network more reliable? Is 4,1V correct when a 5V supply is used?

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    alok2
    Visitor II
    October 4, 2004
    Posted on October 04, 2004 at 02:47

    its an application question. If you think the Vdd rise time is not withinn the LVD spec, choose RC network.

    if the Vdd rise time is within the spec, no problems to use the LVD.

    LVD level of 4.1 on 5V is good enough. You may have to check & analyse the working of other components which are interfaced to the micro when the micro is in reset state but the voltage is available ( before 4.1V in yr case ).
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    bleumers_jAuthor
    Visitor II
    October 4, 2004
    Posted on October 04, 2004 at 05:52

    Thanks for your response.

    VDD risetime is fast enough, so it will be no problem to use the LVD as i'm doïng now. There are no other ''reset-critical'' components interfaced with the MCU.

    In an earlier tread i've read that it there has to be an 10nF cap between the GND and reset pin instead of leaving it floating. Since there are a lot of 100nF caps on this pcb, i'll put use of these for this. I supose 100nF will do fine.

    Greets!
    A
    anshul
    Visitor II
    October 5, 2004
    Posted on October 05, 2004 at 03:48

    Which MCU are you using?

    When using the LVD it is mandatory that you do not connect the pull-up resistance at the reset pin. Also please follow all the recommendations in the datasheet of the MCU which you are using while designing your circuit.

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    bleumers_jAuthor
    Visitor II
    October 5, 2004
    Posted on October 05, 2004 at 05:02

    Hi,

    I'm using an ST7FLITE29. In the datasheet a 10nF cap is recomended between the reset pin and GND. I've added this to the board so now everything should be fine!

    Greets!
    A
    anshul
    Visitor II
    October 5, 2004
    Posted on October 05, 2004 at 09:20

    Also refer section 4 for the cautions.

    ''Caution: During normal operation the ICCCLK pin

    must be pulled- up, internally or externally (external

    pull-up of 10k mandatory in noisy environment).

    This is to avoid entering ICC mode unexpectedly

    during a reset. In the application, even if

    the pin is configured as output, any reset will put it

    back in input pull-up.''
    A
    anshul
    Visitor II
    October 5, 2004
    Posted on October 05, 2004 at 09:20

    Also refer section 4 for the cautions.

    ''Caution: During normal operation the ICCCLK pin

    must be pulled- up, internally or externally (external

    pull-up of 10k mandatory in noisy environment).

    This is to avoid entering ICC mode unexpectedly

    during a reset. In the application, even if

    the pin is configured as output, any reset will put it

    back in input pull-up.''
    B
    bleumers_jAuthor
    Visitor II
    October 5, 2004
    Posted on October 05, 2004 at 12:42

    Ansh, Alok,

    Thanks for your replies.

    The ICC clock pin is indeed connected to the +5V
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