M24C64-R EEPROM ACK behavior confirm,please help to check

[Colin_liu]

Hi experts,

we are developing with ST M24C64-R EEPROM，and take FPGA chip as a IIC controller. we just

implement a byte write and  Random Address Read for test. Both the simulation tool(with ST "M24XXX_Memory.v" verilog module) and oscilloscope wave shows that EEPROM ACK action is not totally matching our understanding.

We take a picture attached to illustrate. We want to know what is presice timing defination as "9th clock pulse period"?

We do not think it is proper to define a clock period at rising/falling edge of SCL(because it may trigger Start/Stop action). But it seems M24C64 EEPROM ACK at the falling edge of SCL.(?)

Could you kindly help to check our understanding ? THANKS.