5. What Hi/Lo voltages are returning to MCU on SPI_MISO? Are those appropriate for your MCU input (Hi & Lo)? How are the data edges looking - are they square or very slow/sloped/delayed compared to when on real power versus GPIO power?
6. Are you familiar with an "eye diagram"? You want a very open eye for your data and clock signals (CLK, MOSI, MISO).
https://www.edn.com/eye-diagram-basics-reading-and-applying-eye-diagrams/
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Given it works at 3.3V but not when powered by the STM32 GPIO, then I'm going back to #1/#3 = Voltage dips. I really think not enough capacitance, especially for fast SPI and EE write.
The voltage dips could be very short, nsec, and difficult to monitor without a very good scope set very carefully to detect small difference, like between 2.6V and 2.2V. Slowing down your data may help detect the issue. Use a zoom on your scope if available to look at all signals during a couple bits (Clk Hi-Lo-Hi-Lo).
** Change: R2/R3 should connect at C1/C2 not GPIO, they need the caps to respond quick.
** What datarate for SPI? I suggest slow till you make it work (100Kbps, not 5Mbps), then speed up, and when you find max then slow down to give a safety margin (10-30%).
So...
a) I take it the 10E in the schematic are 10ohm?
b) Add in parallel to C2 a ceramic 1uF or a ceramic 10uF cap (tantalum better, electrolytic might be too high ESR at 10uF), try for low voltage caps (4V or 6V3) as high voltage might no be same uF at low V.
c) Powerup for longer than 1sec
d) monitor with scope whole time during powerup, you should definitely see a ramp on EE_VCC_pin8 with 10ohm+10uF.
e) Now try your data transfer with the big cap
f) Does it work?
- If yes great, now optimize for smaller caps and faster timing.
- If no then need more data, maybe (1) scope capture when GPIO power and (2) scope capture when real 3V3 power, so can see noise differences. Capture SPI_Clk, SPI_Data, and EE_VCC.
Paul