Message for all curious about end of write interrupt

[radim]

Posted on April 23, 2007 at 13:24

Message for all curious about end of write interrupt

[najoua]

Posted on April 09, 2007 at 11:36

Hello Volius,

Could you please tell me the purpose of the adjustable delay just after the dummy write? The most important is the adjustable delay between enabling the interrupt and disabling it?

Thank you & regards,

Najoua.

[kleshov]

Posted on April 14, 2007 at 03:01

Hi Najoua,

Sorry for replying late.

The idea is to enable the acceptance of the flash interrupt for a short time only to see if the flash IRQ line is asserted in that time window. The length of the second delay defines the size of that window.

I played around with the second delay a bit to choose the best value to highlight the problem; it also gives an indication of the length of the IRQ pulse from the flash controller.

Regards,

- mike

[najoua]

Posted on April 23, 2007 at 09:35

Hello mike,

In your example, APB2 divider factor is DIV2. Could you please try to change this divider (use DIV4 etc...) and the main frequency and tell me their impact on the interrupt occurrence?

Waiting for your feedback,

Best regards,

Najoua.

[kleshov]

Posted on April 23, 2007 at 13:24

I ran a few more test with different CPU and APB clock frequencies. Here are the results:

Code:

CPU/APB(MHz): Result (indices of the non-zero values in triggered[])

---------------------------------------------------------------------

50/25: 82..86 (1 run), 81..85 (3 runs)

37.5/18.75: 60..63 (a few runs)

60/30: {126,128} (1 run), {125,127} (2 runs), {126,127} (2 runs)

50,12.5: {80,82,83} (1 run), 79..83 (2 runs), 80..83 (1 run), {85} (1 run), {81} (1 run), no triggering (2 runs)

50,6.25: no triggering (6 runs)

Regards,

- mike