minimum external clock frequency for CK input

[bob2399]

Posted on September 14, 2006 at 14:00

minimum external clock frequency for CK input

[bob2399]

Posted on September 13, 2006 at 15:56

I am starting up a new board using the STR711FR2T6 microcontroller. Tried to enter DEBUG using the JTAG port (IAR development system) and got ''Memory access timed out ...'' errors. Was running the CK input at 1.8432MHz. Changed it to 4.000MHz and now it worked OK. What is the minimum CK input frequency? Datasheet says it can go down to DC. What is the real limit? :(

[kleshov]

Posted on September 13, 2006 at 16:46

Your JTAG clock frequency (JTCK) must be too high. It cannot exceed a certain fraction of the CPU clock frequency. The datasheet doesn't give any information on that. The following web page suggests that maximum JTAG clock frequency can either be CPU clock times 1 or CPU clock times 1/6:

http://www.segger.com/jlink.html

Try slowing down JTAG clock.

Regards,

- mike

[bob2399]

Posted on September 14, 2006 at 14:00

Thanks for the information, Mike. I had to slow the JTAG clock down to 900KHz to get the JTAG communication running. It still seems a little inconsistant. Sometimes I had to download twice before it actually works, so I still have an issue to investigate, but at least I get start to debug my code. Thanks again! :)