PCLK higher than MCLK ???

[shinnlin]

Posted on November 17, 2004 at 14:05

PCLK higher than MCLK ???

[shinnlin]

Posted on November 16, 2004 at 11:09

User Manual states that PCLK must be equal or lower than MCLK or unexpected behavior may occur.

So, if I use a MCLK lower than PCLK1, ADC interrupt will not occur ??

If so, I will never have a chance to use MCLK lower than 8MHz and get 500Hz ADC sampling rate..

:-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[ :-[

[ This message was edited by: Shinn on 16-11-2004 15:41 ]

[hichem2]

Posted on November 17, 2004 at 14:05

Hi shinn,

It's evident that peripheral clock speed must be equal or lower than CPU clock

speed and you can't have a MCLK lower than PCLK1.In this case (MCLK lower than PCLK1) all the system is perturbed, thus ADC interrupt will not occur. Unexpected behaviour may occur otherwise.

According to the configuration formula of the prescaler register and the limitation of the prescaler factor( see table 56:ADC Prescaler setting)in the reference manual we never have a chance to use MCLK lower than 8MHz and get 500Hz

ADC sampling!! I have tested this and no interrupt is occurred.

Best Regards

HICH ;)