I am working on building a BMS using L9961 IC, based on a research I figured out that in case of fast charging it is suggested to add two or more power MOSFET gates in parallel as seen in the figure below to reduce temperature rise and ensure reliable operation of the power MOSFET. Is there any draw backs for the following configuration ?
Best Regards,
Mohamed Smaili
Welcome @Mohamed_Smaili, to the community!
CHG and DCHG have limited drive currents (data sheet, table 25, IPD = max 85mA), which limits the maximum gate capacitance to be driven (CPRDRV_LOAD = typ. 10nF). If you want to connect MOSFETs in parallel and do not want to use additional gate drivers, please pay particular attention to the exact same type of the MOSFETs at CHG and DCHG, and also to very low gate capacitance of these MOSFETs.
Hope that helps?
Regards
/Peter
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