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Visitor II
May 27, 2003
Question

Pressing RESET (SYSRSTI#->''low'') stops HCLK-PLL

  • May 27, 2003
  • 4 replies
  • 809 views
Posted on May 27, 2003 at 17:57

Pressing RESET (SYSRSTI#->''low'') stops HCLK-PLL

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    4 replies

    moedeker2Author
    Visitor II
    May 23, 2003
    Posted on May 23, 2003 at 12:25

    After powerup everything works fine. My RESET-generator RN5VD (RICOH) generates an reset pulse at power of 130ms. But if I press my reset switch, which generates same pulse at SYSRETI as at powerup, HCLK-PLL stops. 318MHz crystal oscillator is running. No HCLK, PCICLK, MCLK. Power consumption goes down to 40%. I suppose that reading of the straps is the problem. But why?

    Any idea's?

    Bernd

    moedeker2Author
    Visitor II
    May 26, 2003
    Posted on May 26, 2003 at 07:19

    Found the problem: I connected the strap signals DACK_ENC0-2 to an XILINX-CPLD to build DACK signals. The strap pullup value of 470K is overwritten by XILINX internal BUSHOLD-Circuity even that these pins are inputs at the CPLD. After disabling this BUSHOLD-Circuity reset works fine. YIPPI

    Visitor II
    May 26, 2003
    Posted on May 26, 2003 at 23:06

    What STPC are you using? With my STPC Industrial, I sometimes see all the clock signals stop, but not upon a reset. Like if the CPU was executing forbidden code that shuts down the oscillators. I use a MAX705 for reset generation; the reset signal is clean. The only way to reset the CPU is to power down the board.

    moedeker2Author
    Visitor II
    May 27, 2003
    Posted on May 27, 2003 at 17:57

    Sorry I forgot to say: It's an STPC Elite. But I also developed 2 boards with STPC Industrial - a long time ago. I could'nt remember such a problem like yours. Tomorow I will have a look into my old records.