Problem with DMA and VIC. Interruption launched only one time. Again...

[jerome_du_94]

Posted on September 03, 2007 at 06:21

Problem with DMA and VIC. Interruption launched only one time. Again...

[jerome_du_94]

Posted on May 17, 2011 at 09:46

Hello,

I have posted a message about a problem I have with the timer and interruption. Because i can have one interruption, and no more.

I work too with DMA, and it must set an interrupt when it has finish a transfer. And for the first transfer i have an interruption, but not for the others (I'm sure all the transfer are done).

I don't understand. I look a project (AN2442) which work with dma and interruption, and i do the same configuration for DMA and VIC. So, i really don't understand why i have this problem.

Here the initialization code :

Code:

// For VIC

VIC_DeInit(); // Reset values

VIC_Config(DMA_ITLine, VIC_IRQ, 0); // Configure for generate IRQ

VIC_ITCmd(DMA_ITLine, ENABLE); // Active interrupt from DMA

// For DMA

LLI2_InitStruct.LLI_SrcAdd = (u32)((&SSP1->DR)); // Source address is FIFO on SSP1

LLI2_InitStruct.LLI_DesAdd = (u32)(&BufferIn2[0]); // Destination address is the second input buffer

LLI2_InitStruct.LLI_Pointer = 0;

LLI2_InitStruct.LLI_CCR = 0x88240100; // Control Word : transfer of 256 bits SSP

DMA_DeInit(); // Reset values

DMA_StructInit(&DMA_InitStruct); // Initialize structure

DMA_InitStruct.DMA_Channel_LLstItm = (u32)(&(LLI2_InitStruct.LLI_SrcAdd)); // Branch on second LLI

DMA_InitStruct.DMA_Channel_SrcAdd=(u32)((&SSP1->DR)); // Source address is FIFO on SSP1

DMA_InitStruct.DMA_Channel_DesAdd=(u32)(&BufferIn1[0]); // Destination address is the first input buffer

DMA_InitStruct.DMA_Channel_SrcWidth = DMA_SrcWidth_HalfWord;// Source width is 16 bits

DMA_InitStruct.DMA_Channel_DesWidth = DMA_DesWidth_HalfWord;// Destination width is 16 bits

DMA_InitStruct.DMA_Channel_DesBstSize = DMA_DesBst_1Data ; // Source burst transfer request is 1 data

DMA_InitStruct.DMA_Channel_SrcBstSize = DMA_SrcBst_1Data ; // Destination burst transfer request is 1 data

DMA_InitStruct.DMA_Channel_Src = DMA_SRC_SSP1_RX; // DMA is programmed for SSP0 in transmitter

DMA_InitStruct.DMA_Channel_FlowCntrl = DMA_FlowCntrl2_DMA; // The flow controller is the DMA for peripheral to memory transfer (DMA do only ''DMA_Channel_TrsfSize'' transfers, after it load LLI)

DMA_InitStruct.DMA_Channel_TrsfSize = 256; // Transfer size of 256 bytes

DMA_ChannelDESIncConfig(DMA_Channel0, ENABLE); // Increment the destination not the source

DMA_ITConfig(DMA_Channel0, ENABLE); // Active TCIE (Terminal Count Interrupt Enable)

DMA_ITMaskConfig(DMA_Channel0, DMA_ITMask_ITC, ENABLE); // Active ITC (Terminal Count Interrupt Mask)

DMA_Init(DMA_Channel0,&DMA_InitStruct); // Initialize DMA Channel 0

DMA_ChannelCmd (DMA_Channel0,ENABLE); // Enable DMA Channel 0

DMA_Cmd(ENABLE); // Enable DMA -> Launch Transmission

here the interrupt function :

Code:

void DMA_IRQHandler(void)

{

NewFrame++;

DMA_ClearIT(Channel0, DMA_TCC);

}

Help, please, there is something very strange with these interruptions.

[stefano239955_stm1_stmicro]

Posted on May 17, 2011 at 09:46

You have to reconfigure the dma in order to get another irq.

[jerome_du_94]

Posted on May 17, 2011 at 09:46

What do you mean by reconfigure the DMA ?

Normally, the configuration of common registers of DMA don't change when it load an LLI.

And the TCIE bit (bit 32 of CCR) is set to say that interrupts are still enable. And I set this bit.

Code:

LLI2_InitStruct.LLI_CCR = 0x88240100;

No ?

[jerome_du_94]

Posted on May 17, 2011 at 09:46

Yes the VIC is enable.

For DMA, when it has finished his first transfer, it load LLI, so it is reinitialized.

The second transfer is well done, so the DMA is well reinitialized, but the interruption is not handled.

I have a similar problem with timer, so i think there is a problem with the vic, not the DMA. But I don't see what can it be.

[stefano239955_stm1_stmicro]

Posted on May 17, 2011 at 09:46

hi,

did you enable the vic peripheral?

SCU_AHBPeriphClockConfig(__VIC,ENABLE); /*give the clock to VIC.*/

In any case when I wrote ''reconfigure the DMA'' i mean that the dma registers have to be reinitialized after the dma transfer is done

eg.

DMA_Channel0->SRC = YOUR_SRC_ADRESS;

DMA_Channel0->DES = (u32)Your_first_buffer;

/* Set the linked list Items address */

DMA_Channel0->LLI = DMA_Link1[2];

DMA_Channel0->CC = DMA_Link1[3];