program hangs after enabling interrupts

[mtraman]

Posted on April 24, 2007 at 03:54

program hangs after enabling interrupts

[mtraman]

Posted on May 17, 2011 at 09:41

HI,

I use the startup file for RVDK, supplied by ST Micro. For some programs, after executing the statement which changes the processor to system mode and enables the irq and fiq interrupts -

MSR CPSR_c, Mode_SYS ; IRQs & FIQs are now enabled

the processor just goes to some wrong memory location and hangs.

Has anyone faced a similar problem?

Any suggestion is welcome

thanks,

vikram

The code preceeding the statement is given below (91x_init.s)

PRESERVE8

AREA Init, CODE, READONLY

IMPORT |Image$$STACK$$ZI$$Limit| ; imported from scatter-file

IMPORT |Image$$HEAP$$ZI$$Base| ; imported from scatter-file

EXPORT __user_initial_stackheap

; Ensure no functions that use semihosting SWIs are linked in from the C library

; Comment this line if application uses SWI

;IMPORT __use_no_semihosting_swi

; Depending in Your Application, Disable or Enable the following Define

GBLL BUFFERED_Mode ; Work on Buffered mode, when enabling this define

; just enable the Buffered define on 91x_conf.h

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR EQU 0x10

Mode_FIQ EQU 0x11

Mode_IRQ EQU 0x12

Mode_SVC EQU 0x13

Mode_ABT EQU 0x17

Mode_UND EQU 0x1B

Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later

I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled

F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled

;--- BASE ADDRESSES

; System memory locations

RAM_Base EQU 0x04000000

RAM_Limit EQU 0x04018000 ; at the top of 96 KB SRAM

; STR9X register specific definition

SCRO_AHB_UNB EQU 0x5C002034

; --- Amount of memory (in bytes) allocated for stacks

Stack_Base EQU RAM_Limit

USR_Stack_Length EQU 1024

IRQ_Stack_Length EQU 512

SVC_Stack_Length EQU 256

FIQ_Stack_Length EQU 256

ABT_Stack_Length EQU 0

UND_Stack_Length EQU 0

; Add lengths >0 for ABT_Stack, UND_Stack if you need them.

; Offsets will be loaded as immediate values.

; Offsets must be 8 byte aligned.

Offset_FIQ_Stack EQU 0

Offset_IRQ_Stack EQU Offset_FIQ_Stack + FIQ_Stack_Length

Offset_ABT_Stack EQU Offset_IRQ_Stack + IRQ_Stack_Length

Offset_UND_Stack EQU Offset_ABT_Stack + ABT_Stack_Length

Offset_SVC_Stack EQU Offset_UND_Stack + UND_Stack_Length

Offset_USR_Stack EQU Offset_SVC_Stack + SVC_Stack_Length

EXPORT Reset_Handler

ENTRY

Reset_Handler

LDR pc, = NextInst

NextInst

NOP ; execute some instructions to access CPU registers after wake

NOP ; up from Reset, while waiting for OSC stabilization

NOP

NOP

NOP

NOP

NOP

NOP

NOP

IF :DEF: BUFFERED_Mode

; BUFFERED_Mode

; -------------------------------------------------------------------------------

; Description : Enable the Buffered mode.

; When enable, just enable the buffered define on the 91x_conf.h

;

http://www.arm.com/pdfs/DDI0164A_966E_S.pdf

; -------------------------------------------------------------------------------

MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0

ORR r0, r0, 0x8 ; Enable Write Buffer on AHB

MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1

ENDIF

; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,

; when the bank 0 is the boot bank, then enable the Bank 1.

LDR R6, =0x54000000

LDR R7, =0x4

STR R7, [R6]

LDR R6, =0x54000004

LDR R7, =0x3

STR R7, [R6]

LDR R6, =0x5400000C

LDR R7, =0x0

STR R7, [R6]

LDR R6, =0x54000010

LDR R7, =0x20000

STR R7, [R6]

LDR R6, =0x54000018

LDR R7, =0x18

STR R7, [R6]

; --- Enable 96K RAM

LDR R0, = SCRO_AHB_UNB

LDR R1, = 0x0196

STR R1, [R0]

; --- Initialize stack pointer registers

; Enter each mode in turn and set up the stack pointer

LDR r0, =|Image$$STACK$$ZI$$Limit| ; top of stack region

MSR CPSR_c, Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts

SUB sp, r0, Offset_FIQ_Stack

MSR CPSR_c, Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts

SUB sp, r0, Offset_IRQ_Stack

MSR CPSR_c, Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts

SUB sp, r0, Offset_ABT_Stack

MSR CPSR_c, Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts

SUB sp, r0, Offset_UND_Stack

MSR CPSR_c, Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts

SUB sp, r0, Offset_SVC_Stack

; --- Set bits 17-18 of the core Configuration Control Register

MOV r0, 0x60000

MCR p15,0x1,r0,c15,c1,0

; --- Now change to USR/SYS mode and set up User mode stack,

LDR r0, =|Image$$STACK$$ZI$$Limit| ; Top of stack region

MSR CPSR_c, Mode_SYS ; IRQs & FIQs are now enabled

SUB sp, r0, Offset_USR_Stack

[mohamed23]

Posted on May 17, 2011 at 09:41

Hi tvikram,

Is it possible to provide a screenshot of the problem using RVDK ?

this may help to understand where the program hangs.

:-[

Rave

[mtraman]

Posted on May 17, 2011 at 09:41

Thank u for the reply. I am really desperate to clear this bug.

The screen shots are attached

The file is just the startup file - 91x_init.s

The problem is some unknown interrupt that occurs as soon as the interrupts are enabled in CPSR register of the core.

After this interrupt, which looks like irq the processor always branches to 0x00000018. The flash has been erased and the content at 0x18 is 0xFFFFFFFF which is not a legal instruction. So, the processor stops there.

Also, this occurs for the programs where atleast one peripheral interrupt is enabled.

Thank u,

Vikram

[mtraman]

Posted on May 17, 2011 at 09:41

Only now i realised that no matter what memory we use, when an irq occurs the processor always goes to 0x18 (flash). this implies that no one can run programs that use interrupts, with an empty flash. Also, it means that the irq handler should be located at 0x18.

placing vect.o at the start of ram has no effect as only the handler at 0x18 will be used anyway. This also answered my earlier question of unused vect.o while using ram, posted in ''91x_vect.s does not change''.

Moderator please correct me if i am wrong.

If i am right i am surprised that so many in the forum don,t know this or didn't bother to answer.

Moderator please correct me if i am wrong.

Vikram