Smart Card Interface Rx Problem

[lukas239955_st]

Posted on May 31, 2006 at 22:30

Smart Card Interface Rx Problem

[lukas239955_st]

Posted on May 24, 2006 at 05:47

Hi all

I seem to have some issue with the SC interface. I'm running the UART1 in smart card mode. After a card has been inserted I enable the clock, wait >40000 clk cycles (according to standard) and then drive the card reset high. The card then correctly sends the ATR on SCDATA (checked on the oscilloscope).

However, in the UARTs RXBUF register I always receive 0x1FF i.e. FF with a parity error. Looks like the STR710 sees a startbit somewhere and then begins to sample the idle line before the card actually transmitts the ATR. I already checked that the receiver is enabled only after the IO line has reached a stable high state.

Configuration is as follows:

SCCLK: 4MHz

Baudrate: 10750

Uart mode: SC enabled, 8 bit, even parity, 1.5 stopbits, fifo/loopback disabled.

Any ideas?

Regards Lukas

[daweiy]

Posted on May 31, 2006 at 22:30

After pull the reset high, there has a minimum delay t1, no less than 380 clock cycles. Do you wait it?