SPI issue regarding its running speed

[lillian_200601]

Posted on November 26, 2008 at 13:00

SPI issue regarding its running speed

[lillian_200601]

Posted on May 17, 2011 at 09:55

Hi All,

I am using Keil MCBSTR9 evaluation board with STR912FAW44X6 to run the SPI program. The external device runs as a master and MCBSTR9 as a slave. The issue is that SPI program can work properly at Fpllclk 48 Mhz, but cannot work at Fpllclk 96MHz.

The SPI demo program (SPI0 as a master and SPI1 as a salve) from ST website can work at 96Mhz.

Anybody has any clue and suggestions how I can run the SPI program at 96 Mhz. Greatly appreciate any help.

Lillian

[matthew239955_stm1]

Posted on May 17, 2011 at 09:55

Did you change anything besides doubling the fmaster clock?

I would suspect two things:

1) First, double check that you have the correct clock phase, polarity, etc. set to match your master device. You may be only marginally working at 48 Mhz bc of incorrect configuration.

2) Next, when you double the pll clock, are you dividing down your pclk and brclk values to match your old settings? If not, try to change the divide down values on those clocks to get a brclk & pclk equal to the values you are running at a pll of 48 Mhz. This might zero in on the problem.

And not to continue to harp on this, but please try to be more descriptive than ''cannot work''. What is the specific behavior? Does the program receive data, but it is the wrong value? Does it never trigger a receive interrupt? etc. Posting code helps too. This helps others diagnose the problem, prevents wild guesses, and gets a resolution to your problem without having to go through multiple rounds of questions.

[lillian_200601]

Posted on May 17, 2011 at 09:55

Thanks a lot Mattew for your suggestions. Sorry for my late response. I am busy on other stuff after I posted my question. Now I am back.

1) First, double check that you have the correct clock phase, polarity, etc. set to match your master device. You may be only marginally working at 48 Mhz bc of incorrect configuration.

A: I double check the Master configuration and my slave device is set the same configuration as Master device.

// VIC1 configuration

VIC_DeInit();

VIC_Config(SSP0_ITLine, VIC_IRQ, 2);

VIC_ITCmd(SSP0_ITLine, ENABLE);

/* SSP0 configuration , SSP0 is slave */

SSP_DeInit(SSP0);

SSP_InitStructure.SSP_FrameFormat = SSP_FrameFormat_Motorola;

SSP_InitStructure.SSP_Mode = SSP_Mode_Slave;

SSP_InitStructure.SSP_CPOL = SSP_CPOL_Low;

SSP_InitStructure.SSP_CPHA = SSP_CPHA_2Edge;

SSP_InitStructure.SSP_DataSize = SSP_DataSize_8b;

SSP_InitStructure.SSP_ClockRate = 5;

SSP_InitStructure.SSP_ClockPrescaler = 2;

SSP_InitStructure.SSP_SlaveOutput = SSP_SlaveOutput_Enable;

SSP_Init(SSP0, &SSP_InitStructure);

/* Enable SSP0 receive interrupt */

SSP_ITConfig(SSP0, SSP_IT_RxTimeOut, ENABLE);

/* SSP0 enable */

SSP_Cmd(SSP0, ENABLE);

2) Next, when you double the pll clock, are you dividing down your pclk and brclk values to match your old settings? If not, try to change the divide down values on those clocks to get a brclk & pclk equal to the values you are running at a pll of 48 Mhz. This might zero in on the problem.

A: SPI program can work properly at either 96 Mhz or 48 Mhz if only SPI program is downloaded into STR912 microprocessor. However, the SPI can only run at 48 Mhz(Fpllclk)when the USB and SPI program are combined together. The SPI will have strange behaviour if I set the Fpllclk to 96Mhz.

Under 96Mhz setting, I divide the pclk and brclk by 2 based on your suggestions. But I don't understand why I need to change brclk. I also divide FMICLK by 2. In the very beginning, the master device can get correct data. After a few seconds, the MISO pin from slave starts sending wrong data to the Master device.

/*Set_System */

SCU_MCLKSourceConfig(SCU_MCLK_OSC);

FMI_Config(FMI_READ_WAIT_STATE_2,FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE,FMI_FREQ_HIGH);

SCU_PLLFactorsConfig(192,25,2);

SCU_PLLCmd(ENABLE);

SCU_MCLKSourceConfig(SCU_MCLK_PLL);

SCU_AHBPeriphClockConfig(__VIC,ENABLE);

SCU_AHBPeriphReset(__VIC,DISABLE);

/*USB clock = MCLK= 48MHz*/

SCU_USBCLKConfig(SCU_USBCLK_MCLK2);

SCU_PCLKDivisorConfig(SCU_PCLK_Div2);

SCU_FMICLKDivisorConfig(SCU_FMICLK_Div2);

SCU_BRCLKDivisorConfig(SCU_BRCLK_Div2);

What is it wrong with my configuration? Greatly appreciate any help.

Lillian