SPI question

[henrik239955]

Posted on March 29, 2006 at 06:18

SPI question

[henrik239955]

Posted on March 28, 2006 at 06:08

In my application I use SPI interface to transfer data between a ST7234 and a STLITE09. ST7234 is master and LITE09 acts as slave. What happens if a false clock pulse occurs on the SCK line (in a noisy environment for example)? The communication will be out of sync until new reset? Is there any way to recover from this without re-start the slave?

BR

bood

[info45]

Posted on March 28, 2006 at 19:09

Hy,

You don't have problems with spike on clock, IF and only IF the Chip select on SPI slave is inactive (high state).

Bye

[henrik239955]

Posted on March 29, 2006 at 05:48

Thanks for reply. I dont get your point. No matter how you manage chip select I think there is a risk of spikes when the chip is selected?

Chip select (SS) on my slave is managed by software and allways active (0).

bood

[info45]

Posted on March 29, 2006 at 06:13

Hy Bood,

I prefer manage slave SS active only during spi communication.

So I have a hw/sw robustness: spike on signals are allowed without desyncronization.

If in Your application need to keep slave SS low, then Your hw/sw is spike sensible....

Bye

[henrik239955]

Posted on March 29, 2006 at 06:18

OK, thank you.