SSP Slave Mode - SSP0_MISO not high impedence when CS high

[gu48bz]

Posted on June 14, 2007 at 15:09

SSP Slave Mode - SSP0_MISO not high impedence when CS high

[gu48bz]

Posted on May 17, 2011 at 09:43

Hi Guys,

I've got a bit of a teaser here. Using rev G silicon, I've enabled the SSP mode as Motoralla format, Slave mode, based on 4 wire comms.

The comms itself is working fine, all data clocked in and out is correct.

The problem being is that there is another serial device on the SPI bus and its serial data out is getting stuffed, as the ARM's SSP0_MISO is not going high impedence when the chip select is high (low=chip selected).

I looked through the datasheet and it says that if the chip is not selected, then the serial out should go high impedence.... it doesn't!

To ensure chip select is working, I hard wire it high. The ARM stoped transmitting on the output and also no longer received data on the input, even though the clock line is active.... good!

Anyone got any ideas on this one?

Cheers

Steve

[ This message was edited by: stevesky on 02-06-2007 15:58 ]

[gu48bz]

Posted on May 17, 2011 at 09:43

Having tried as many combinations, I've come to the conclusion that this is *another* silicon issue. Workaround is use an external tri-state buffer enabled using the chip select.