ST7LITE49M_output compare mode problems(please help)

[anniyan_x]

Posted on September 18, 2008 at 01:01

ST7LITE49M_output compare mode problems(please help)

[anniyan_x]

Posted on September 17, 2008 at 09:41

hi im using ST7lite49M mcu for my project,facing a problem on the output compare mode.im using output compare mode for UART TX RX. im using the 12bit autoreload timer in output compare mode.my TX works fine but problem comes wn im sampling in the RX data frm PC. the output compare match seems interrupts at different timing..or the timing seems drifting away...stime it working fine and stime it not working..the outcompare stime seems not generating interupt according to the DCR values tht is loaded.at reset,i iniatilizing the outcompare interrupt enable,then load the DRC values.after the first outcompare match interrupt..i reload the DRC value,set the TRANSbit and set FORCE overflow bit.i think im doin according to the datasheet but seems my output is not stable and stime works and stime not..most of time the timing would be larger than the loaded DRC values. so im really not sure where or what is goin wrong...so could anyone guide me or tell me the standard procedure to enable and iniatile output compare mode and make periodic interrupt. it like im facing synchronization problems...

[ This message was edited by: anniyan_x on 17-09-2008 13:15 ]

[anniyan_x]

Posted on September 18, 2008 at 01:01

some new informations(attached code and optionbyte screen shot)

Im using RIDE as the toolchain and im trying to reach the 4M frequency, previous I had trying to divide my internal RC which is 8M to 4M but then I cant set the transmission and receiving at 9600bps but Transmission work fine in 4800bps and Receiving is not stable. Later then I didn’t set the internal RC division by two. I just set as Frc = Fcpu, and this the transmission can work at 9600bps but the receiving is not accurate and not stable, stime can work properly and stime cant receive. Anyway my target frequency is 4M. Im using the REVA starter kit(v2.1) and im using 3.3v power supply from the reva board itself. I have attached a screenshot of my option byte settings. Im setting the MCU according to the block diagram only im not setting anything in the SICSR registers.

the output compare mode is working but still not stable and always the sampling timing drift aways frm the actually setting…the timing seems to be correct at the first bit wn I sample the start bit(middle of the bits) I load half bit delay and wn the output compare interrupt occurs I sample the start and the middle of the bit and if ok I load the DCR values for full bit delay so tht I can sample the next bit on its middle, and set the TRANS bit and FORCE overflow and 2nd output compare match occur correctly at the middle and after that onwards the timing seem to have a delay or an added abt 80us to the actually delay and the timing drifts and finally it start to sample at wrong timings and the reading are wrong. And the other problem as I told at reset the output compare timing was totally wrong and from the 2nd match interrupt it works although stime it is unstable. but this problem I solved(I think I have solved) by setting the TRANSxbit in the “main.c�? and just FORCE overflow at the main before entering the “while loop�?.

[ This message was edited by: anniyan_x on 18-09-2008 04:35 ]

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Attachments :

codes.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I05E&d=%2Fa%2F0X0000000bTw%2FxGb6sRWQzp_nApl02TNAWLKbMBTs_4x1Clk2CHXuzVs&asPdf=false

optionbyte.JPG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hzgy&d=%2Fa%2F0X0000000bTx%2FX7_g6MHCRmC7ji5q5zHJPhzb1Q5390lXgUjHqF28mrs&asPdf=false