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Visitor II
March 16, 2005
Question

ST92F150 with external SRAM 32K: problems

  • March 16, 2005
  • 3 replies
  • 854 views
Posted on March 16, 2005 at 05:41

ST92F150 with external SRAM 32K: problems

    This topic has been closed for replies.

    3 replies

    siegmundAuthor
    Visitor II
    May 17, 2011
    Posted on May 17, 2011 at 11:36

    Hi professionals,

    we're using the ST92F150CV1 for about 18months in production (about 1000 pieces). Suddenly we have problems with the external SRAM: it's no more possible to write data in it.

    Facts:

    CPU-Speed: 12MHz, Core-Speed: 6MHz, DS-strecht: MAX, AS-Strech: MAX

    mode control: Mode=0, ETO=off, BSZ=1,

    circuit as in ST9-Datasheet V4, page 143, mode=0

    ram: div. manufacturers (samsung, issy), 70ns and 55ns

    the messured cycle-time is about 1usec (very slow!)

    playing with waitstates, different configurations, different rams shows no way to fix the problems.

    on some boards reducing waitstates (as/ds) brings success, but not on the others. mode=1 (with rewiring AS to ALE) brings success on one board, but not on the others.

    are there any known (but inofficial) timing-probs with the EMI?

    (such as the new chapter ''KNOWN LIMITATIONS'' in datasheet V4?

    (app notes an1069 + an1076 are well known).

    has anybody successfull created a board with such a configuration?

    need help!

    siegmundAuthor
    Visitor II
    May 17, 2011
    Posted on May 17, 2011 at 11:36

    Hi,

    it seems to be a timing-problem with R/W.

    in mode=1 (and removing the inverter for AS->ALE) the sram runs perfectly.

    unfortunately, we can't switch the design to mode=1, cause on the same data/adressbus there's a graphic-LCD which doesn't run with mode=1.

    And: sram should work with mode=0 (as shown in datasheets)! :-W

    anybody any hints?

    siegmundAuthor
    Visitor II
    May 17, 2011
    Posted on May 17, 2011 at 11:36

    hi there,

    another facts (problem is still existing):

    i attached diagramms of 4 accesses to the sram:

    2x write:

    - write AD=2, Data=1

    - write AD=3, Data=2

    2x read

    - read AD=2: >> Data=3 (fail!!!)

    - read AD=3: >> Data=2 (correct)

    why doesnt work the first write?

    the naming conventions are for sram, the mode in st9 is mc=0 (oe/ which is ds/ from st9 has one cycle in mc=0).

    and, as you can see in the diagramms, all waitstates are activated, so access is slow.

    what is wrong in first write-access?

    thank you professionals!

    siggi