Startup and Linker files

[ewald]

Posted on August 29, 2006 at 20:49

Startup and Linker files

[ewald]

Posted on May 17, 2011 at 09:31

Does anybody have a simple Startup- and linker file for the GNU-Compiler?

Maybee with a smal c-Programm?

regards

ED

[stefano239955_stm1_stmicro]

Posted on May 17, 2011 at 09:31

The Hitex HITOP for arm has an example of gcc for str9.

You can download the demo version where you can find the demo for str9.

The

http://www.raisonance.com/

has a GCC toolchain with some demo

for STR9.

I attached the demo project for Hitex where you can find startup.s and linker file.

I suggest you to compared the startup.s file with the iar one.

some initialization in the gcc version are missing like:

#ifdef BUFFERED_Mode

; BUFFERED_Mode

; -------------------------------------------------------------------------------

; Description : Enable the Buffered mode.

; When enable, just enable the buffered define on the 91x_conf.h

;

http://www.arm.com/pdfs/DDI0164A_966E_S.pdf

; -------------------------------------------------------------------------------

MRC p15,0,r0,c1,c0,0 ; Read CP15 register 1 into r0

ORR r0, r0, #0x8 ; Enable Write Buffer on AHB

MCR p15,0,r0,c1,c0,0 ; Write CP15 register 1

#endif

; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,

; when the bank 0 is the boot bank, then enable the Bank 1.

LDR R6, =0x54000000

LDR R7, =0x4

STR R7, [R6]

LDR R6, =0x54000004

LDR R7, =0x3

STR R7, [R6]

LDR R6, =0x5400000C

LDR R7, =0x0

STR R7, [R6]

LDR R6, =0x54000010

LDR R7, =0x20000

STR R7, [R6]

LDR R6, =0x54000018

LDR R7, =0x18

STR R7, [R6]

; --- Enable 96K RAM

LDR R0, = SCRO_AHB_UNB

LDR R1, = 0x0196

STR R1, [R0]

; --- Reset VIC controller

LDR R0, = SCR0_AHB_PER_UNB

LDR R1, [R0]

ORR R1, R1, #VIC_RES_BIT

STR R1, [R0]

; --- Disable any source of interupt // used in debug mode

LDR R0, = VIC0_BASE

LDR R1, =0xFFFFFFFF

STR R1, [R0, #VICx_INTECR]

LDR R0, = VIC1_BASE

STR R1, [R0, #VICx_INTECR]