STNRGPF01 related questions

[Iliescu Mihai]

Hello,

I found a problem in eDesignSuite when i try to use STNRGPF01 (PFC boost interleaved IC).

At input current sensing the ICS Target Voltage is 3.00V and in the datasheet the ICS Target Vltage looks like it is 1.25V (also in the Help section of eDesignSuite). Which one is correct?

Also, is there any other datasheet (maybe we need to sign an NDA for it or smth like that) because the one on the site is very poor.

Best regards,

Mihai I.

[Carmelo VICCICA]

Hi Mihai,

Thank you for your interest in ST Portofolio.

About your question.

The information on the "Help" is older and refers to the first version of the proposed solution, so please refer to the information in the ICS wizard.

Thank you for reporting, we will update this information on the next version, which should be released by 2018.

If you have specific questions or concerns, you can use the ST community for assistance.

Regards.

Carmelo

[Iliescu Mihai]

Hello @Carmelo VICCICA​ 

Thanks a bunch for your answer! It is the first time i get an answer about problems regarding that IC..

What about the datasheet? There is written 1.25V max for this type of input.

The datasheet is also wrong?

Best regards,

Mihai

[Carmelo VICCICA]

Hi Mihai,

In short 1.25V are a limitation on inside comparator present in this family products, as specified in pag 32 (table 14) of datasheet (https://www.st.com/resource/en/datasheet/stnrgpf01.pdf)

So every time user have necessity to compare a signal using internal comparator, the pin should have following range 0-1,25Volts.

This is the golden rule, in solution proposed, applied on

- Input Voltage Sensing Circuit,

- Output Voltage Sensing Circuit,

- Output Current Sensing Circuit,

where output go directly to a STNRGPF01's pin for comparision.

On the contrary on  Input Current Sensing Circuit, the output of this module is a input for PI regulator so only in this case we can use a different target voltage according to the IC used in the Current Control Loop (https://www.st.com/resource/en/datasheet/lmv321.pdf).

The two resistors R58 and R62, between PI's output and OUT_PIN, give a scale factor of 0.635 that ensure the correct voltage on OUT_PIN pin.

For further information on the proposed solution, it is also possible to refer to the following link, which shows a case of real use for STNRGPF01.

https://www.stmicroelectronics.com.cn/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/psu-and-converter-solution-eval-boards/steval-ipfc01v1.html

I hope my answer has been exhaustive.

Regards.

Carmelo.

[Iliescu Mihai]

Hello @Carmelo VICCICA​ .

You're right, i don't know how i did missed that. Thank you very much!

But i got a few more questions, if you are kind enough to help me:

1. At the input crrent sensing circuit, RMS current is ok, but the peak current is huge, i got a 3kW design, for calculating the RMS current on shunt resistor, formula is Pout_total/(Eff*Vline_min*PF), Pout total is the maximum power (in my case 3kW), Eff - efficiency, in my case 95% and PF is the power factor, in my case 0.99. This result in about 16.8A. This is what designsuite shows for maximum current also, but the problem is that it says that the maximum current should be 31.82A, and i don't know how it could be. Maybe if you didn't have any soft start-up and your current would only be limited by the capacitors resistance. Can you explain that? I will attach a photo also.
2. Another question is about maximum output voltage of the PFC. You can calculate with a ripple of 5%, given that your output will be, let's say at 380V, and you can get a maximum of ~399V, but the maximum output voltage is stated as 426V. In the description of that maximum output voltage it says something like this is the mximum voltage that the PFC can reach in any conditions, but i am not sure what are those conditions..
3. In the datasheet the pins R[1]...R[4] are reserved, but in the steval-ipfc01v1, the pins are tied with the switch current readings, what is the "correct" way?

Thanks for your time and best regards,

Mihai I.

[Carmelo VICCICA]

Hi Mihai,

Thanks for your questions, I will try to answer them.

About first question on ICS circuit:

The maximum peak current on R144 is calculate by following formulas

Ipeak = Irms * Math.sqrt(2) ( 1 + ripple/n) * margin

where :

• ripple is Acutal current ripple percentage (value taken from Boost Inductor Page) ~0,69
• n is Number of Channel = 3
• margin : marging factor to protect sistem = 1,05

with previous formula Ipeak is always 1,83 x Irms

About second question on Maximum Output Voltage:

In Interleaved PFC Specification in Output Section you find

• Nominal Output Voltage (Vout) = 400V
• Output Voltage ripple = 20V (=> Vout * 5/100) with standard ripple at 5%
• Maximum Voltage = 448V => Vout * (1+ 0.12) where 0.12 is a margin factor

About "Help" on  Maximum Voltage a review will be done in the future release

About third question on R[x] Pin:

datasheet is wrong. it will be updated in the future release.

We apologize for inaccurate documentation and will try to update it with the next version of the product that will be released shortly.

Best Regards.

Carmelo Viccica

[Iliescu Mihai]

Hello @Carmelo VICCICA​,

Thanks a lot for your answer, for the second and third questions i understood. For the first one i understood what is the formula but it doesn't make much sense. Anyway, i will use it as it is, and will come back with much more details after the first prototype testing.

I got another question (i will use your link - https://www.st.com/resource/en/data_brief/steval-ipfc01v1.pdf for the schematic).

In the 4th page, where is the comparator circuit (U304) your negative input is ~ VDD(5V)*10k/(10k+3k3) = 3.75V. The input of the comparator is maximum 1.25V(-0.3 or -0.4 from the diode) so how it can ever switch?

On the design suite, the resistor divider it is correct.

So, you have RocpL/(RocpL+RocpH) x VDD => 5*1.8/11.8 = 0.70V - that's correct.

So, i guess your board kit has a mistake?

Best regards,

Mihai

[Carmelo VICCICA]

Hi Mihai,

We apologize for the delay in the reply, but we are engaged in other projects.

The documentation present in website refers to STEVAL-IPFC01V1 where all OP Amplifier are supplied with 5V, so the input of U304 will be have a range from [0 - 4,7V].

eDesignSuite refers to a previous version of board where all OP Amplifier are supplied with 3V (EVAL-IPFC01V1).

In the future eDesignSuite will be updated to match with actual documentation of STEVAL-IPFC01V1.

Both designs are correct according to supply voltage selected for IC.

Best Regards.

Carmelo Viccica

[Iliescu Mihai]

Hello,

Sorry to bother, but i am in almost the final stage of the first iteration of the PFC using your IC and i my only ST support right now it is this forum (actually, you) because the datasheet has very little information about anything...

Ok, now that makes sense.

Thanks a bunch and best regards,

Mihai

[Iliescu Mihai]

Hello,

@Carmelo VICCICA​ 

Any update? I am almost in the final design phase and this is a major problem.

Best regards,

Mihai

[Iliescu Mihai]

 Hello again @Carmelo VICCICA​ ,

I got another question about your STEVAL board.

Here you can see that the output of U304 - an output of 5V is going directly into the IC (OCP[1] - which is a 1.25V maximum allowed) how that the chip still works?

Another question is about the ZVD signal and circuit, because it looks very strange and even in simulation i don't understand how it does work. I guess that it should give a pulse on the ZVD pin every time the signal is 0 (given that is rectified by that diode D102). But why those two resistance (R108 and R109)?

Thanks a bunch and best regards,

Mihai

[Carmelo VICCICA]

Hi Mr. Iliescu

about your questions, below you can find some clarification how system works.

Q: "Here you can see that the output of U304 - an output of 5V is going directly into the IC (OCP[1] - which is a 1.25V maximum allowed) how that the chip still works?"

R: In case of consecutive OCP events, C333 is charged until the FAULT voltage level (1.23 V) is reached on OCP[1] PIN 28 of the STNRGPF01. At this point the system is stopped so the voltage cannot increase above 1.23 V, but in any case the pin is 5V tolerant so no problem.

Q: Another question is about the ZVD signal and circuit, because it looks very strange and even in simulation i don't understand how it does work. I guess that it should give a pulse on the ZVD pin every time the signal is 0 (given that is rectified by that diode D102). But why those two resistance (R108 and R109)?

R: Resistors R105, R108 and R109 limit the sensing current at few mA while R106 sets the voltage for a correct conduction of the optocoupler’s diode.

 During the positive half-cycle, diode D102 is directly polarized and optocoupler is turned on, so the capacitor C101 is charged and ZVD voltage is clamped to VDD-VCEsat. During the negative half-cycle optocoupler is open, hence capacitor is discarged through R110 and ZVD voltage is equal to GND.

Best Regards.

Carmelo Viccica

[Iliescu Mihai]

Hello,

Thank you very much for your explanation!

Best regrds,

Mihai

[Iliescu Mihai]

Hello all members of ST community and happy new year!

I got a question regarding the STNRGPF01, is there any way to disable the burst mode under no load or light load condition? (<5%) I don't need and i don't want (actually, the burst mode could be a really big problem in this case...) to have burst mode when no load.

Best regards,

Mihai I.

[Iliescu Mihai]

@Carmelo VICCICA​  - any ideas about the question above?

Hello all members of ST community and happy new year!

I got a question regarding the STNRGPF01, is there any way to disable the burst mode under no load or light load condition? (<5%) I don't need and i don't want (actually, the burst mode could be a really big problem in this case...) to have burst mode when no load.

Best regards,

Mihai I.

[Carmelo VICCICA]

Hi Mr. Iliescu,

about your question, the answer is negative.

There is no possibility to disable the burst mode.

Regards.

Carmelo Viccica