STPC Elite Interrupt problem - stuck IRQ0 ISR bit

[gary239955_st]

Posted on October 14, 2005 at 19:06

STPC Elite Interrupt problem - stuck IRQ0 ISR bit

[gary239955_st]

Posted on October 14, 2005 at 14:09

I wrote about this problem in a previous post and it is still plaguing us. To date we have spent well over 2 months analyzing this problem, but due to the highly integrated nature of the STPC we have not been able to pinpoint a cause.

We have a custom designed STPC Elite-based board running the PharLap ETS version 10.1 operating system and a General Software BIOS version 4.30.

Our system timer tick is set at 1millisec. So IRQ0 (Timer0) interrupts are occuring every 1 millisec. Our system does power-system measurement computations every 1/4 cycle (of 60Hertz) so we have a group of IRQ9 (DSP DMA) interrupts occuring approximately every 4.167milliseconds. In addition, it should be noted that during the failure mode our application thread is enabling and disabling 486 interrupts quite frequently.

Our problem is that after several hours of operation the interrupt system ''locks up''. In this mode we observe that the ISR bit for IRQ0 (Timer0) and the IRR bit for IRQ9 (DSP DMAs) are active, but the system did not vector to the IRQ0 interrupt service routine. As such, IRQ0 ISR bit does not get cleared and so no other interrupts can (or will) occur.

Is it possible there is a mode inside the STPC whereby it gets confused (sets the ISR bit but does not generate the interrupt vector) while receiving two interrupts at the same time while the 486 interrupt enable (IE) bit is either being enable or disabled?

We monitor all other interrupts, including the spurious interrupts (IRQ7 and IRQ15), and NONE of them go active during this failure mode.

We detect that the IRQ0 ISR bit active while running in application code. My understanding is that as long as the EOI command is getting issued correctly during the Interrupt Service Routine, the ISR bit should only be active while executing Interrupt Service Routine code and NOT application code.

The documentation for the 8259A states that the ISR bit is set during the first Interrupt Acknowledge (INTA) pulse from the 486 to the interrupt controller. During the second Interrupt Acknowledge (INTA) pulse is when the 486 obtains the interrupt vector. Is it possbile that the 486 Interrupt Enble (IE) is being set or cleared between the two INTA pulses and subsequently misses the interrupt vector transfer?

Please help!

Thank you.

[gary239955_st]

Posted on October 14, 2005 at 19:06

I'd also like to mention that the DSP DMA transfer just prior to the IRQ0 (Timer0) and IRQ9 (DSP DMA) interrupts consumes the PCI bus for a finite amount of time since our DSP processor communicates to the STPC over the PCI bus.

Is it possible that this is preventing the 486 core from communicating to the interrupt controller (on the ISA bus) in order to service the IRQ0 interrupt in a timely fashion?

Depending on how the STPC prioritizes PCI bus activity, is it possible the two 486 interrupt acknowlege (INTA) cycles are getting interrupted by the DSP DMA transfers?

Thanks again.