STPC VEGA double write cycle on PCI bus

[granitvt]

Posted on July 26, 2006 at 04:18

STPC VEGA double write cycle on PCI bus

[granitvt]

Posted on June 06, 2006 at 05:43

I have double write cycle, when i try programm flash memory (AM29DL323�?¡ (AMD)) on PCI bus of the embedded module, based on STPC VEGA processor. It happens seldom (about one time in ~2000 write cycles). The similar situation was described in item 8 ''STPC VEGA Errata List'', but with reference to read operation. I disable interrupts before issue command sequence for programm operation, but i still have a double write cycles. I check it on 3 processors STPC VEGA. Can somebody tell me about this problem solution?

[kaouther]

Posted on June 06, 2006 at 11:35

Could you to disable the PCI write posting feature in the bios and then program the flash?

[granitvt]

Posted on June 07, 2006 at 05:29

I've found in ''STPC VEGA Programming Manual ver. 3.0'' write posting control bits for data transfer from PCI to Host Memory, IDE to Host Memory and ISA to Host Memory. But I did not found write posting control bit for data transfer from Host to PCI. Can you tell me where can I find describing of the control bits for write posting from Host (CPU) to PCI?

[kaouther]

Posted on June 07, 2006 at 09:58

Yes it is the write posting control bits for data transfer from PCI to Host Memory. You can disable it in the Bios setup configuration.

there is no write posting from Host to CPU. Could you test it?

[granitvt]

Posted on June 07, 2006 at 10:05

Yes, I've tested it. All that bits cleared (write posting disable). I need control bits for write posting from Host to PCI, not Host to CPU!

[kaouther]

Posted on June 07, 2006 at 10:30

Sorry it was spelling mistake. I mean from HOST to PCI.

you need to disable only the PCI Write Posting in the NORTH BRIDGE CONTROL REGISTER Bit20.

There is no control bits from PCI to HOST.

Whis this feature disabled ''all memory write cycles from PCI to host are

allowed to complete before the PCI cycle is terminated and all burst

write attempts will be disconnected on the PCI bus.''

You are able to programm the flash even with this feature disabled.

[granitvt]

Posted on June 21, 2006 at 03:37

I've disabled all write posting feature (clear all bits), but I've see on digital analyzer rare double write cycles (on issue command sequence for flash programm operation). Can somebody to offer another solution this problem? Thanks.

[granitvt]

Posted on July 26, 2006 at 04:18

There are NO double write cycle on PCI bus if I use PCI 2.0 in North AND South bridge in Vega !!! What is it? I'll read in STPC BIOS Writer's Guide p. 3.4: ''The PCI 2.1 protocol introduced retry cycles, which allow a target to indicate to a master that it is not ready to send or receive data'', but I didn't found PCI 2.0 specification. I know that PCI 2.1 difference from PCI 2.0 multiple bus mastering, more slots, 64bit, 66MHz, but I didn't found about retry cycle on PCI 2.0. Can somebody tell me about retry cycle on PCI 2.0?