STR 750 I2C error handling

[jpeacock2]

Posted on July 14, 2008 at 23:25

STR 750 I2C error handling

[jpeacock2]

Posted on June 27, 2008 at 20:12

Has anyone managed to get an interrupt driven I2C handler working, with error recovery for events such as bus errors or non-existent device? The ST example for I2C is woefuly inadequate, and the STR750 manual has virtually no information on how to recover from errors, especially a bad device address (a common occurence when enumerating devices on a common bus).

Ad hoc experiemnting shows that the AF flag is sometimes set (SR1 = 0x10, SR2 = 0x92) when a device does not respond, but this doesn't seem to happen consistently. At times I get both SR1 and SR2 set to zero in interrupts, no idea how this happens since there's no interrupt source. It doesn't occur when a valid device is found.

Perhaps there's some errata on the I2C bus?

[jrheisey]

Posted on July 14, 2008 at 23:25

I was wondering whether you got you ISR based I2C communications to work.

I have implemented an ISR to track I2C errors. I've been trying to debug this but I am not seeing the issue. Here is my ISR function

Code:

void RmiOverI2c::I2cISR(void)

{

g_uStatus = I2C_GetStatus(I2C1);

I2C_FlagClear (I2C1, I2C_EVF);

if(g_uStatus & I2C_AF) {

CI2c_Pulse(10)

I2C_FlagClear (I2C1, I2C_AF);

}

else if(g_uStatus & I2C_BERR) {

CI2c_Pulse(20)

}

else if(g_uStatus & (I2C_AF | I2C_BERR)) {

CI2c_Pulse(15)

}

}

The ISR routine is being called from a standard IAR IRQHandler in 71x_vect.s. My problem is that the EVF won't clear even though I2C_GetStatus() accesses CR, SR1 and SR2 which is suppose to clear most if not all flags according to the STR711 reference. I watch the registers for I2C1 and do not see any changes.

Thanks,

J.R.