STR710FZ2 MCU and M48Z512AV NVRAM connection diagram

[akar]

Posted on August 31, 2006 at 11:14

STR710FZ2 MCU and M48Z512AV NVRAM connection diagram

[akar]

Posted on August 31, 2006 at 06:03

Dear moderator,

I have written a program with STR710 Evaluation board.

The program works wery well. Now, I want to use ST M48Z512AV NVRAM

instead of CY7C1069 SRAM. I already made my prototype board.

I need the connection diagram, because I confused why ST did not use the address 0 pin? Please could you send us the connection diagram for these?

Thank you very much.

[davidbellegarde9]

Posted on August 31, 2006 at 09:21

Hello,

The address 0 is not used on the STR71x eval board schematic because 2 x 2M x 8bit are used. And 2 x 2M x 8bit is the same as 2M x 16bit. And with 16 bit memory on EMI, the A0 is useless.

If you want to map only one ST M48Z512AV NVRAM, you should connect the A0 pin and configure the EMI as well.

Regards,

[akar]

Posted on August 31, 2006 at 11:14

Hello squirrel,

I changed one of the CY7C1069 sram with a M48Z512AV nvram from my prototype board, and connected address 0 pin.

How can I do the EMI setup for use the nvram as alone?

My startup code is below.

#define EMI_base_addr 0x6C000000 // EMI base address

#define BCON0_off_addr 0x00 // Bank 0 configuration register offset

#define BCON1_off_addr 0x04 // Bank 1 configuration register offset

#define BCON2_off_addr 0x08 // Bank 2 configuration register offset

#define BCON3_off_addr 0x0C // Bank 3 configuration register offset

#define EMI_ENABLE 0x8000

#define EMI_SIZE_16 0x0001

#define GPIO2_base_addr 0xE0005000 // GPIO2 base address

#define PC0_off_addr 0x00 // Port Conf. Register 0 offset

#define PC1_off_addr 0x04 // Port Conf. Register 1 offset

#define PC2_off_addr 0x08 // Port Conf. Register 2 offset

#define PD_off_addr 0x0C // Port Data Register offset

// EMI INITIALIZE

LDR r0, =GPIO2_base_addr // Configure P2.0->3 in AF_PP mode

LDR r2, [r0, #PC0_off_addr]

ORR r2, r2,#0x0000000F

STR r2, [r0, #PC0_off_addr]

LDR r2, [r0, #PC1_off_addr]

ORR r2, r2,#0x0000000F

STR r2, [r0, #PC1_off_addr]

LDR r2, [r0, #PC2_off_addr]

ORR r2, r2,#0x0000000F

STR r2, [r0, #PC2_off_addr]

LDR r0, =EMI_base_addr

LDR r1, =0x18 | EMI_ENABLE | EMI_SIZE_16

STR r1, [r0, #BCON1_off_addr] // Enable Bank1 16-bit 7-waitstate

SRAM start address 0x62000000

Thank you very much for your concern.