STR71x Reference manual Revision History

[kaouther]

Posted on October 10, 2007 at 13:02

STR71x Reference manual Revision History

[kaouther]

Posted on October 10, 2007 at 13:02

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Dear,

New revision of STR71x Reference manual Rev1 is available for download from the web site;

http://www.st.com/mcu/familiesdocs-86.html

Here below, changes compared to the last revision UM0084 (Rev8);

+ Created new document RM0002 to replace UM0084 and restart revision numbering.

+ Modified section 1.3.4: ''Write access examples'' Figure3 and Figure 5:

- 1.5*tMCLK between address valid and the assertion of both nCS and nRD.

+ Updated Section 2.6.2: ''Clock flag register (RCCU_CFR)''

- Bits 14:11 ; read/clear write 1 instead of read/clear write 0.

+ Modified Section 3.1.3: ''Alternate function I/O (AF)''.

- For alternate function inputs, the port must be configured in Input

mode and the input pin must be driven externally.

+ Added Section 5.3.4: ''RTC flag assertion''

- Added Note: If RTC interrupts are used during Run, Slow, WFI or LPWFI modes the RTC clock must beat least 4 times slower than PCLK2 clock. However, it still possible to use the RTC alarm but through the XTI interrupt (XTI Line15).

+ Updated Section 5.4.3: ''RTC prescaler load register high (RTC_PRLH)''

- These bits are used to define the counter clock frequency according to the following formula: fTR_CLK = fRTC/(PRL[19:0]+1).

- Caution: The zero value is not recommended, otherwise RTC interrupts and flags cannot be asserted correctly.

+ Updated Section 5.4.4: ''RTC prescaler load register low (RTC_PRLL)''

- These bits are used to define the counter clock frequency according to the following formula: fTR_CLK = fRTC/(PRL[19:0]+1.

- Added Note; If the input clock frequency(fRTC) is 32.768 kHz, write 7FFFh in this register to get a signal period of 1 second.

+ Updated Section 10.7: ''Start-up status''

- The MSTR bit must be set high and then the BSPI must be enabled.

+ Updated Section 11.4.7: ''UART guardtime register (UARTn_GTR)''

- Bits 15:8 are reserved.

+ Updated Section 13.5.2 ''13.5.2 System and power-on reset''

- Added USB startup time.

+ Updated Section 15.2: ''APB Software Reset Register (APBn_SWRES)''

- Added Table 54 APB1 peripherals and Table 55 APB2 peripherals.

Best Regards.

[ This message was edited by: coucou on 13-10-2007 14:59 ]