STR9 internal FLASH bank1 for data storage problems

[info80]

Posted on February 13, 2007 at 06:35

STR9 internal FLASH bank1 for data storage problems

[info80]

Posted on May 17, 2011 at 09:36

Hallo

I'm using functions from ST-Bibrary or Keil Flash-driver. I want to erase sector and write datas in this sector. With both I've the result, that the flash-functions do there work, but my application-software stops or collapse.

With breakpoints after erase-commands it functions correctly.

Has anybody an idea or an example, how to use internal flash from STR9?

Thanks for help

[hd2]

Posted on May 17, 2011 at 09:36

Hi,

I've been having the same problems. Apparently there are some erratas we should look at.

1. Rev D silicon has a limitation with regards to the FMI clock during erase and program. The FMI clock should be limited to 25MHz. Please see Section 2.21 in the Errata. This is corrected with later revs of the silicon.

2. There is an errata related to a system reset at 96MHz (see section 2.19). If the debugger asserts a system reset with the FMI clock set to 96MHz, some strange results may happen afterwards. In this case, a power-cycle is required (a press of the reset switch will not help). Rev E and later revs do not have this issue.

3. The flash memory requires 2 wait states when executing code with the FMI clock set to 96MHz. Before switching the FMI clock to 96MHz, the flash memory must be set for 2 wait states. Setting the wait states is done by issuing a command to the flash through a bank 1 address (see section 1.13.4 Flash Configuration Register in the flash programming manual). When executing code out of bank 1, this register can't be written to as it basically takes the flash offline and it can't be accessed.

Your problem sounds most closley related to #1 above.

Good Luck

[hd2]

Posted on May 17, 2011 at 09:36

Hi,

I've been having the same problems. Apparently there are some erratas we should look at.

1. Rev D silicon has a limitation with regards to the FMI clock during erase and program. The FMI clock should be limited to 25MHz. Please see Section 2.21 in the Errata. This is corrected with later revs of the silicon.

2. There is an errata related to a system reset at 96MHz (see section 2.19). If the debugger asserts a system reset with the FMI clock set to 96MHz, some strange results may happen afterwards. In this case, a power-cycle is required (a press of the reset switch will not help). Rev E and later revs do not have this issue.

3. The flash memory requires 2 wait states when executing code with the FMI clock set to 96MHz. Before switching the FMI clock to 96MHz, the flash memory must be set for 2 wait states. Setting the wait states is done by issuing a command to the flash through a bank 1 address (see section 1.13.4 Flash Configuration Register in the flash programming manual). When executing code out of bank 1, this register can't be written to as it basically takes the flash offline and it can't be accessed.

Your problem sounds most closley related to #1 above.

Good Luck

[info80]

Posted on May 17, 2011 at 09:36

Thanks for the hint.

It was the problem with too high clock like in errata 2.21 explained.

Thank you