str9 startup code

[sjo]

Posted on August 31, 2006 at 07:46

str9 startup code

[sjo]

Posted on May 17, 2011 at 09:30

I notice that all the ST examples using IAR compiler use the following to configure the bank0/1 sizes/addresses at reset.

; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,

; when the bank 0 is the boot bank, then enable the Bank 1.

LDR R6, =0x54000000

LDR R7, =0x4 <== should be 6

STR R7, [R6]

LDR R6, =0x54000004

LDR R7, =0x3 <== should be 2

STR R7, [R6]

LDR R6, =0x5400000C

LDR R7, =0x0

STR R7, [R6]

LDR R6, =0x54000010

LDR R7, =0x20000 <== should be 0x80000

STR R7, [R6]

LDR R6, =0x54000018

LDR R7, =0x18

STR R7, [R6]

looking at the register description and comments i get the different values for the config above.

Config above is for a STR91xFx44 device.

Could someone confirm i am correct or misreading the ref manual.

Regards

sjo

[alain239955_st]

Posted on May 17, 2011 at 09:30

The manual is not very clear on those point

LDR R6, =0x54000000

LDR R7, =0x4 <-- This correct because bootBank size is 64K * 2^0x4 = 512K

STR R7, [R6]

LDR R6, =0x54000004

LDR R7, =0x3 <== should be 2 <- So far I understand, You are righ 8K * 2^2 = 32K

STR R7, [R6]

LDR R6, =0x5400000C

LDR R7, =0x0

STR R7, [R6]

LDR R6, =0x54000010

LDR R7, =0x20000 <== should be 0x80000 <-- NO the address are specifed in 4 bytes word

STR R7, [R6]

LDR R6, =0x54000018

LDR R7, =0x18

STR R7, [R6]

Regards

[anis]

Posted on May 17, 2011 at 09:30

Hi acorchia, Sjo,

I agree with you , the flash configuration section is not very clear in reference manual.

The correct flash configuration when Bank0 is the boot bank is:

LDR R6, =0x54000000

LDR R7, =0x4 -> BootBank size is: 32K * 2^0x4 = 512K

STR R7, [R6]

LDR R6, =0x54000004

LDR R7, =0x2 -> NonBootBank size is: 8K * 2^2 = 32K

STR R7, [R6]

** 0x3 was used in the IAR example because there is an issue with rev B of STR9 where you need to configure Bank1 as 64K , but for rev D and later, you need to put 0x2 (please refer to STR9 errata sheet v2.0 paragraph 2.1 for more details).

LDR R6, =0x5400000C

LDR R7, =0x0 -> boot bank address: 0X0

STR R7, [R6]

LDR R6, =0x54000010

LDR R7, =0x20000 ***

STR R7, [R6]

*** non boot bank address : 0x80000, but it should be shifted by 2 because Flash bus address A[23:0] is connected to CPU bus address A[25:2].

LDR R6, =0x54000018

LDR R7, =0x18 -> enable banks

STR R7, [R6]

Best regards,

STARM