sytem reset at 96 MHz

[heiko23]

Posted on November 03, 2006 at 16:56

sytem reset at 96 MHz

[heiko23]

Posted on May 17, 2011 at 09:33

Hi!

I tried a system reset at 96Mhz.

But the CPU never comes from the reset. Only after power up.

In the errata sheet for STR91xF Controller I found that the FMI Clock must be configured to run at 48 MHz.

I have made this but the problem is still there.

Have I made somthhing wrong?

/* Enable VIC clock */

SCU_AHBPeriphClockConfig(__VIC, ENABLE);

VIC_DeInit();

SCU_RCLKDivisorConfig(SCU_RCLK_Div1); // RCLK Div 1 = 96Mhz

SCU_HCLKDivisorConfig(SCU_HCLK_Div1); // HCLK Div 1 = 96MHz

SCU_PCLKDivisorConfig(SCU_PCLK_Div1); // PCLK Div 1 = 96 MHz

SCU_FMICLKDivisorConfig(SCU_FMICLK_Div2);

FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_1,

FMI_PWD_ENABLE, FMI_LVD_ENABLE,FMI_FREQ_LOW);

SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */

SCU_PLLCmd(ENABLE); /* PLL Enabled */

SCU_MCLKSourceConfig(SCU_MCLK_PLL); // Master Clock = 96 MHz

Can anyone help me?

Silicon Rev D Date Code 610

[roger_lynx]

Posted on May 17, 2011 at 09:33

I have made this but the problem is still there.

 

Have I made somthhing wrong?

 

 

/* Enable VIC clock */

 

SCU_AHBPeriphClockConfig(__VIC, ENABLE);

 

VIC_DeInit();

 

 

SCU_RCLKDivisorConfig(SCU_RCLK_Div1); // RCLK Div 1 = 96Mhz

 

SCU_HCLKDivisorConfig(SCU_HCLK_Div1); // HCLK Div 1 = 96MHz

 

SCU_PCLKDivisorConfig(SCU_PCLK_Div1); // PCLK Div 1 = 96 MHz

 

Yes, the PCLKDivisor has to yield a resulting maximum frequency of 48 MHz.

So, 96 MHz coming out from PLL (f_MSTR) has to be divided by two.

See data sheet, page 15.

I use this for 96 MHz:

SCU_RCLKDivisorConfig(SCU_RCLK_Div1);

SCU_PCLKDivisorConfig(SCU_PCLK_Div2);

SCU_HCLKDivisorConfig(SCU_HCLK_Div1);

Hope this helps.