Timer interrupt flag clear problem

[gupta2]

Posted on June 21, 2012 at 10:27

Hi..

We are using STR912FAW44 and keil 3 as IDE. We are using TIM0 in OCM1 mode with OC1 interrupt enabled.We are using a counter inside the interrupt, Interrupt count time is 100 ms, we have to measure 900 seconds, so checking when counter will become 9000. If we clear interrupt status flag at the end of the ISR then no problem, but if  interrupt status flag is cleared in the beginning of the ISR, then interrupt time becomes exactly half, means counter reaches 9000 value in approx 4500 seconds. Any idea regarding this.???

[Pantuca.Erwin]

Posted on June 22, 2012 at 06:45

i would suggest to review the assembler code generated.  we have had one issue with the arm compiler set at full optimization making a mess of our timer interrupt code (apparently skipping some line).  the intended logic of the C code was not followedm  although the c code was also in the first place stgrange like multiple resets of the same flag, the person who made this is not part of our team anymore i cannot ask him why, we just leave it like it is for now as long as it works.

[gupta2]

Posted on June 27, 2012 at 11:28

[Pantuca.Erwin]

Posted on June 27, 2012 at 14:31

we may not have a similar function as yours.  we clear our ocf always at the end of the timer interrupt handler function.

sorry i dont see your source code so we can only answer in general.  

we follow AN2593 Str91x interrupt management.pdf.

your problem is similar to that of the interrupt triggered twice, mentioned in the other discussion.  do you manually re-enable the I-bit? such as for nested interrupt?  i have found one possible similar issue regarding this case:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/3682.html