UART+TIME0

[netz]

Posted on September 21, 2007 at 07:42

UART+TIME0

[netz]

Posted on September 19, 2007 at 12:53

Hello,

I've sent this Question to just another thread, because of the

similar issue.

Perhaps here is the right place.

I have got TIM0-Int for 1ms regularly.

It works for so long, I don't get an RX-Int.

After running the Rx_IRQ-Handler, the Timer has the OCFA/OCAIE-

bits are set, but the Int is never served.

my 71x_vec.s has the history-date:;* 13/01/2006 : V3.1

Any Idea?

Steffen

[netz]

Posted on September 20, 2007 at 06:20

[netz]

Posted on September 20, 2007 at 06:27

i some more information.

I work with the IAR-Compiler and the softwarelib

history tag: 13/01/2006 : V3.1

The issue is:

I get 1ms ticks regularly, until there is a UART-RX-IRQ.

Thereafter, there is no TIM0-IRQ.

If I single-step it works fine?!

The first question, Can I stop the clock during

break in C-Spy.

When I single step through this lines:

IRQHandler

SUB lr,lr,#4 ; Update the link register

SaveContext r0,r12 ; Save the workspace plus the current

; return address lr_ irq and spsr_irq.

LDR lr, =ReturnAddress ; Read the return address.

LDR r0, =EIC_base_addr

LDR r1, =IVR_off_addr

ADD pc,r0,r1 ; Branch to the IRQ handler.

ReturnAddress:

; Clear pending bit in EIC (using the proper IPRx)

LDR r0, =EIC_base_addr

LDR r2, [r0, #CICR_off_addr] ; Get the IRQ channel number.

MOV r3,#1

MOV r3,r3,LSL r2

STR r3,[r0, #IPR_off_addr] ; Clear the corresponding IPR bit.

RestoreContext r0,r12 ; Restore the context and return to the...

; ...program execution.

The EIC_IPR0_0 won't be reset on the line :STR r3...

Is this right?

My Config looks like:

EIC_IRQChannelPriorityConfig(T0TIMI_IRQChannel, INT_PRIO_TIM0); // priority from 1 to 15 ( low to high)

/* enables global IRQ handling of EIC */

EIC_IRQConfig(ENABLE);

/* Enable Timer IRQ in interrupt controller */

EIC_IRQChannelConfig(T0TIMI_IRQChannel, ENABLE);

/* Initialize the Timer 1 registers to reset values */

TIM_Init ( TIM0 );

/* Configure the Timer 1 Prescaler */

TIM_PrescalerConfig ( TIM0, 0x00 );

/* Enable the Output Compare interrupt for the Timer 1 */

TIM_ITConfig ( TIM0, TIM_OCA_IT, ENABLE );

/* configure and enable Timer 1 */

TIM_OCMPModeConfig ( TIM0, TIM_CHANNEL_A, 0xFFFF, TIM_TIMING, TIM_HIGH );

and the Int:

void T0TIMI_IRQHandler(void)

{

GPIO2->PD |= BIT14;

/*Clear the TIM1 interrupt flag Bit 14 OCFA */

TIM_FlagClear(TIM0, TIM_OCFA);

/* set next time to generate an interrupt */

/* to achieve 1ms at 24Mhz input frequency */

/* the value is set to 24000 ticks */

TIM0->OCAR += 3000;

OSTimer();

GPIO2->PD &= ~BIT14;

}

Hopefully,

Steffen

[netz]

Posted on September 20, 2007 at 12:15

OK,

it was my fault. The error was in the UART-Tx.

The problem is with the TXHalfempty-Flag.

It is set after Reset, though in the reference is

stated:

â—� TxHalfEmpty is activated when data is moved from UARTn_TxBUFR to the txshift

register.

I understood this wrong.

regards,

S.Netz

[kaouther]

Posted on September 21, 2007 at 07:42

The statement in the reference manual (TxHalfEmpty is activated when data is moved from UARTn_TxBUFR to the txshift register.) this is regarding the interrupt corresponding to TxHalfEmptyIE (Transmitter buffer Half Empty Interrupt Enable) and not the TxHalfEmpty flag.

However , you have to refere to section (11.3.1 Transmission) instead and you can find details about the TxHalfEmpty flag.

''If the fifos are enabled, UARTn_SR(TxHalfEmpty) is set when the TxFIFO contains 8 or fewer characters. If the fifos are disabled, the TxHalfEmpty flag set when the TxFIFO is empty.'' and it is set after reset.

Regards.