Viper 26LD loosing regulation

[vitor1]

Posted on July 02, 2016 at 12:44

Hi,

 I have used eDesign to implement viper on my application. My specs are input voltage 70Vdc to 160Vdc / output 15Vdc (5.1W). For some reason, the viper 26LD is loosing regulation (when connecting to a load) - the output voltage decreases as the load increases. Furthermore, I heard buzz coming out of it. After replacing the component a few times, the buzz stopped but I still didn't get the right output voltage.

You may find attached the schematics!

Thanks in advance for your support. 

#retification #viper-26ld

[Patrizia BELLITTO]

Posted on September 15, 2016 at 15:25

Try to review your board according to these basic layout design rules:

- Keeping power loops as confined as possible. The area circumscribed by current loops where high pulsed current flow should be minimized to reduce its parasitic self-inductance and the radiated 

electromagnetic field. In a buck converter the most critical loop is the one including the input bulk capacitor, the VIPer, the power inductor, the output capacitor and the free-wheeling diode. When designing  

the layout, the above said components should be the first one to be placed, trying to put as close as possible to each other. Then the power traces connecting them should be drawn, in order to minimize

  the area circumscribed by the resulting loop; NO components should be placed inside this loop.

   After that, the signal components can be placed and the signal traces can be designed.

- Separating signal from power tracks. Traces carrying signal currents should run far from others carrying pulsed currents or with fast swinging voltages. In case of two-layer PCB, it is a good  

 practice to route signal traces on one PCB side and power traces on the other side.

   Furthermore, Signal ground traces and power ground traces should be kept separate from each other, and finally connected directly to the GND pin of the VIPer.

 The compensation network should be connected to the COMP, maintaining the trace to GND as short as possible.

- Filtering sensitive pins. A low ESL ceramic capacitor (a few hundreds pF up to 0.1 μF) should be connected across VCC and GND, placed as close as possible to the IC.

- Reducing line lengths. All traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and wide as possible, to keep both resistive and inductive effects to a minimum.

- Optimizing track routing. Since Vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them in the power path.

- Improving thermal dissipation. An adequate copper area has to be provided under the DRAIN pins as heatsink, while it is not recommended to place large copper areas on the GND.