Why can not access a 10ns SRAM in less than 25ns with the STR710?

[jdonate]

Posted on January 19, 2007 at 07:10

Why can not access a 10ns SRAM in less than 25ns with the STR710?

[jdonate]

Posted on January 18, 2007 at 15:01

Hi, I’m working with the STR710 and right now the program is too big for the internal flash, so I have decided to move the program to external memory. The problem is the speed, I need a lot. So I’m using Thumb mode with a 16bit 10ns access time SRAM memory and a 64MHz MCLK. With this configuration I need at least 1 wait state to access memory correctly, which is 30ns. Changing clock I’ve seen the fastest I cold go is 25ns access time, but I can no even understand why. The Sram it’s right and also with the oscilloscope I see data is fast enough, but for some reason the STR7 is not capable to read it. Also the control, address and data path is straight, there is not interface logic between STR7 and memory.

Using the STR7 eval board from ST, and using the 10ns cypress SRAM memories, I have the same problem, so I think is not a signal or routing problem.

Any Ideas?

[jgoril]

Posted on January 19, 2007 at 04:32

Hello. Look at UM0084 (STR71x Microcontroller reference manual), page 20. Having 0 wait states defined, there are 2 cycles (measured in EMI internal clocks unit) needed to perform single memory access. Having 64MHz clock, one cycle takes 15.6ns, giving 31.2ns access time. So... here your 30ns come from...

Jozef

[jgoril]

Posted on January 19, 2007 at 04:38

...for those 2 cycles - they come from ARM7TDMI core memory interface. You can find more in ARM7TDMI TRM, chapter 3.3 - Bus cycle types. :)

[jdonate]

Posted on January 19, 2007 at 06:26

I all ready know that. What I mean is this, since CE goes down until CE goes it is 15.62 ns, which is the access time. That’s the time I’m referring, not the total time to read data, which is as you said 31.2ns. The thing is that my SRAM is 10ns access time, so from CE going down to Data present on the output there is no more than 10ns. With 0 wait states, the STR7 have 15.62 ns until it reads data, but in that case it reads wrong data. I need 1 wait state, which means an access time of 30.2ns from the SRAM point of view, but that makes no sense, also when looking with the oscilloscope the signals are in the right places, I mean, with 0 wait states, if I look to D0 and with the debugger I try to read one position of the SRAM, the oscilloscope shows a logic 1 5ns before CE rises, but the STR7 reads a logic 0. That’s what I can not understand.

[kleshov]

Posted on January 19, 2007 at 07:01

The datasheet says that Read Data Setup Time is 22 ns minimum. That should explain it.

- mike

[jdonate]

Posted on January 19, 2007 at 07:08

Finally I´ve got my answer. Looking in detail in the EMI timming on pdf 10350, I saw the Read Setup Time is 22ns minimum ( which is a lot, but it is what it is). That´s the parameter that I was needing to take into account. And also figuer 26 on page 57 of 10350.pdf doc is the really one that helps to understand the whole proccess.

Thanks to Opijozko anyway.

[jdonate]

Posted on January 19, 2007 at 07:10

Thanks to Mike too, I was writting the answer to myself when you were posting yours. :D